
#ifndef	_HTC_H_
#warning Header file pic16f7x7.h included directly. Use #include <htc.h> instead.
#endif


 /* header file for the MICROCHIP PIC microcontrollers
  * PIC16F737
  * PIC16F747
  * PIC16F767
  * PIC16F777
 */

#ifndef	__PIC16F7X7_H
#define	__PIC16F7X7_H

// Special function register definitions

static volatile       unsigned char	TMR0		@ 0x01;
static volatile       unsigned char	PCL		@ 0x02;
static volatile       unsigned char	STATUS		@ 0x03;
static                unsigned char	FSR		@ 0x04;
static volatile       unsigned char	PORTA		@ 0x05;
static volatile       unsigned char	PORTB		@ 0x06;
static volatile       unsigned char	PORTC		@ 0x07;
#if defined(_16F747) || defined(_16F777)
static volatile       unsigned char	PORTD		@ 0x08;
#endif
static volatile       unsigned char	PORTE		@ 0x09;
static volatile       unsigned char	PCLATH		@ 0x0A;
static volatile       unsigned char	INTCON		@ 0x0B;
static volatile       unsigned char	PIR1		@ 0x0C;
static volatile       unsigned char	PIR2		@ 0x0D;
static volatile       unsigned char	TMR1L		@ 0x0E;
static volatile       unsigned char	TMR1H		@ 0x0F;
static volatile       unsigned char	T1CON		@ 0x10;
static volatile       unsigned char	TMR2		@ 0x11;
static volatile       unsigned char	T2CON		@ 0x12;
static volatile       unsigned char	SSPBUF		@ 0x13;
static volatile       unsigned char	SSPCON		@ 0x14;
static volatile       unsigned char	CCPR1L		@ 0x15;
static volatile       unsigned char	CCPR1H		@ 0x16;
static volatile       unsigned char	CCP1CON		@ 0x17;
static volatile       unsigned char	RCSTA		@ 0x18;
static volatile       unsigned char	TXREG		@ 0x19;
static volatile       unsigned char	RCREG		@ 0x1A;
static volatile       unsigned char	CCPR2L		@ 0x1B;
static volatile       unsigned char	CCPR2H		@ 0x1C;
static volatile       unsigned char	CCP2CON		@ 0x1D;
static volatile       unsigned char	ADRESH		@ 0x1E;
static volatile       unsigned char	ADCON0		@ 0x1F;
static          bank1 unsigned char	OPTION		@ 0x81;
static volatile bank1 unsigned char	TRISA		@ 0x85;
static volatile bank1 unsigned char	TRISB		@ 0x86;
static volatile bank1 unsigned char	TRISC		@ 0x87;
#if defined(_16F747) || defined(_16F777)
static volatile bank1 unsigned char	TRISD		@ 0x88;
static volatile bank1 unsigned char	TRISE		@ 0x89;
#endif
static          bank1 unsigned char	PIE1		@ 0x8C;
static          bank1 unsigned char	PIE2		@ 0x8D;
static volatile bank1 unsigned char	PCON		@ 0x8E;
static volatile bank1 unsigned char	OSCCON		@ 0x8F;
static          bank1 unsigned char	OSCTUNE		@ 0x90;
static volatile bank1 unsigned char	SSPCON2		@ 0x91;
static          bank1 unsigned char	PR2		@ 0x92;
static          bank1 unsigned char	SSPADD		@ 0x93;
static volatile bank1 unsigned char	SSPSTAT		@ 0x94;
static volatile bank1 unsigned char	CCPR3L		@ 0x95;
static volatile bank1 unsigned char	CCPR3H		@ 0x96;
static volatile bank1 unsigned char	CCP3CON		@ 0x97;
static volatile bank1 unsigned char	TXSTA		@ 0x98;
static          bank1 unsigned char	SPBRG		@ 0x99;
static          bank1 unsigned char	ADCON2		@ 0x9B;
static volatile bank1 unsigned char	CMCON		@ 0x9C;
static volatile bank1 unsigned char	CVRCON		@ 0x9D;
static volatile bank1 unsigned char	ADRESL		@ 0x9E;
static          bank1 unsigned char	ADCON1		@ 0x9F;
static volatile bank2 unsigned char	WDTCON		@ 0x105;
static volatile bank2 unsigned char	LVDCON		@ 0x109;
static volatile bank2 unsigned char	EEDATL		@ 0x10C;
/* Alternate definition for backward compatibility */
static volatile bank2 unsigned char	EEDATA		@ 0x10C;
static          bank2 unsigned char	EEADRL		@ 0x10D;
/* Alternate definition for backward compatibility */
static          bank2 unsigned char	EEADR		@ 0x10D;
static volatile bank2 unsigned char	EEDATH		@ 0x10E;
static          bank2 unsigned char	EEADRH		@ 0x10F;
static volatile bank3 unsigned char	EECON1		@ 0x18C;

/* Definitions for memory access */
static          unsigned char bank2	PMDATA		@ 0x10C;
static          unsigned char bank2	PMDATL		@ 0x10C;
static          unsigned char bank2	PMADRL		@ 0x10D;
static 	        unsigned char bank2	PMDATH		@ 0x10E;
static 	        unsigned char bank2	PMADRH		@ 0x10F;
static          unsigned char bank3	PMCON1  	@ 0x18C;


/* Definitions for STATUS register */
static volatile       bit	CARRY		@ ((unsigned)&STATUS*8)+0;
static volatile       bit	DC		@ ((unsigned)&STATUS*8)+1;
static volatile       bit	ZERO		@ ((unsigned)&STATUS*8)+2;
static volatile       bit	PD		@ ((unsigned)&STATUS*8)+3;
static volatile       bit	TO		@ ((unsigned)&STATUS*8)+4;
static                bit	RP0		@ ((unsigned)&STATUS*8)+5;
static                bit	RP1		@ ((unsigned)&STATUS*8)+6;
static                bit	IRP		@ ((unsigned)&STATUS*8)+7;

/* Definitions for PORTA register */
static volatile       bit	RA0		@ ((unsigned)&PORTA*8)+0;
static volatile       bit	RA1		@ ((unsigned)&PORTA*8)+1;
static volatile       bit	RA2		@ ((unsigned)&PORTA*8)+2;
static volatile       bit	RA3		@ ((unsigned)&PORTA*8)+3;
static volatile       bit	RA4		@ ((unsigned)&PORTA*8)+4;
static volatile       bit	RA5		@ ((unsigned)&PORTA*8)+5;
static volatile       bit	RA6		@ ((unsigned)&PORTA*8)+6;
static volatile       bit	RA7		@ ((unsigned)&PORTA*8)+7;

/* Definitions for PORTB register */
static volatile       bit	RB0		@ ((unsigned)&PORTB*8)+0;
static volatile       bit	RB1		@ ((unsigned)&PORTB*8)+1;
static volatile       bit	RB2		@ ((unsigned)&PORTB*8)+2;
static volatile       bit	RB3		@ ((unsigned)&PORTB*8)+3;
static volatile       bit	RB4		@ ((unsigned)&PORTB*8)+4;
static volatile       bit	RB5		@ ((unsigned)&PORTB*8)+5;
static volatile       bit	RB6		@ ((unsigned)&PORTB*8)+6;
static volatile       bit	RB7		@ ((unsigned)&PORTB*8)+7;

/* Definitions for PORTC register */
static volatile       bit	RC0		@ ((unsigned)&PORTC*8)+0;
static volatile       bit	RC1		@ ((unsigned)&PORTC*8)+1;
static volatile       bit	RC2		@ ((unsigned)&PORTC*8)+2;
static volatile       bit	RC3		@ ((unsigned)&PORTC*8)+3;
static volatile       bit	RC4		@ ((unsigned)&PORTC*8)+4;
static volatile       bit	RC5		@ ((unsigned)&PORTC*8)+5;
static volatile       bit	RC6		@ ((unsigned)&PORTC*8)+6;
static volatile       bit	RC7		@ ((unsigned)&PORTC*8)+7;

#if defined(_16F747) || defined(_16F777)
/* Definitions for PORTD register */
static volatile       bit	RD0		@ ((unsigned)&PORTD*8)+0;
static volatile       bit	RD1		@ ((unsigned)&PORTD*8)+1;
static volatile       bit	RD2		@ ((unsigned)&PORTD*8)+2;
static volatile       bit	RD3		@ ((unsigned)&PORTD*8)+3;
static volatile       bit	RD4		@ ((unsigned)&PORTD*8)+4;
static volatile       bit	RD5		@ ((unsigned)&PORTD*8)+5;
static volatile       bit	RD6		@ ((unsigned)&PORTD*8)+6;
static volatile       bit	RD7		@ ((unsigned)&PORTD*8)+7;

/* Definitions for PORTE register */
static volatile       bit	RE0		@ ((unsigned)&PORTE*8)+0;
static volatile       bit	RE1		@ ((unsigned)&PORTE*8)+1;
static volatile       bit	RE2		@ ((unsigned)&PORTE*8)+2;
#endif
static volatile       bit	RE3		@ ((unsigned)&PORTE*8)+3;

/* Definitions for INTCON register */
static volatile       bit	RBIF		@ ((unsigned)&INTCON*8)+0;
static volatile       bit	INT0IF		@ ((unsigned)&INTCON*8)+1;
static volatile       bit	TMR0IF		@ ((unsigned)&INTCON*8)+2;
static                bit	RBIE		@ ((unsigned)&INTCON*8)+3;
static                bit	INT0IE		@ ((unsigned)&INTCON*8)+4;
static                bit	TMR0IE		@ ((unsigned)&INTCON*8)+5;
static                bit	PEIE		@ ((unsigned)&INTCON*8)+6;
static                bit	GIE		@ ((unsigned)&INTCON*8)+7;

/* Definitions for PIR1 register */
static volatile       bit	TMR1IF		@ ((unsigned)&PIR1*8)+0;
static volatile       bit	TMR2IF		@ ((unsigned)&PIR1*8)+1;
static volatile       bit	CCP1IF		@ ((unsigned)&PIR1*8)+2;
static volatile       bit	SSPIF		@ ((unsigned)&PIR1*8)+3;
static volatile       bit	TXIF		@ ((unsigned)&PIR1*8)+4;
static volatile       bit	RCIF		@ ((unsigned)&PIR1*8)+5;
static volatile       bit	ADIF		@ ((unsigned)&PIR1*8)+6;
#if defined(_16F747) || defined(_16F777)
static volatile       bit	PSPIF		@ ((unsigned)&PIR1*8)+7;
#endif

/* Definitions for PIR2 register */
static volatile       bit	CCP2IF		@ ((unsigned)&PIR2*8)+0;
static volatile       bit	CCP3IF		@ ((unsigned)&PIR2*8)+1;
static volatile       bit	BCLIF		@ ((unsigned)&PIR2*8)+3;
static volatile       bit	LVDIF		@ ((unsigned)&PIR2*8)+5;
static volatile       bit	CMIF		@ ((unsigned)&PIR2*8)+6;
static volatile       bit	OSFIF		@ ((unsigned)&PIR2*8)+7;

/* Definitions for T1CON register */
static                bit	TMR1ON		@ ((unsigned)&T1CON*8)+0;
static                bit	TMR1CS		@ ((unsigned)&T1CON*8)+1;
static                bit	T1SYNC		@ ((unsigned)&T1CON*8)+2;
static                bit	T1OSCEN		@ ((unsigned)&T1CON*8)+3;
static                bit	T1CKPS0		@ ((unsigned)&T1CON*8)+4;
static                bit	T1CKPS1		@ ((unsigned)&T1CON*8)+5;
static                bit	T1RUN		@ ((unsigned)&T1CON*8)+6;

/* Definitions for T2CON register */
static                bit	T2CKPS0		@ ((unsigned)&T2CON*8)+0;
static                bit	T2CKPS1		@ ((unsigned)&T2CON*8)+1;
static                bit	TMR2ON		@ ((unsigned)&T2CON*8)+2;
static                bit	TOUTPS0		@ ((unsigned)&T2CON*8)+3;
static                bit	TOUTPS1		@ ((unsigned)&T2CON*8)+4;
static                bit	TOUTPS2		@ ((unsigned)&T2CON*8)+5;
static                bit	TOUTPS3		@ ((unsigned)&T2CON*8)+6;

/* Definitions for SSPCON register */
static                bit	SSPM0		@ ((unsigned)&SSPCON*8)+0;
static                bit	SSPM1		@ ((unsigned)&SSPCON*8)+1;
static                bit	SSPM2		@ ((unsigned)&SSPCON*8)+2;
static                bit	SSPM3		@ ((unsigned)&SSPCON*8)+3;
static                bit	CKP		@ ((unsigned)&SSPCON*8)+4;
static                bit	SSPEN		@ ((unsigned)&SSPCON*8)+5;
static volatile       bit	SSPOV		@ ((unsigned)&SSPCON*8)+6;
static volatile       bit	WCOL		@ ((unsigned)&SSPCON*8)+7;

/* Definitions for CCP1CON register */
static                bit	CCP1M0		@ ((unsigned)&CCP1CON*8)+0;
static                bit	CCP1M1		@ ((unsigned)&CCP1CON*8)+1;
static                bit	CCP1M2		@ ((unsigned)&CCP1CON*8)+2;
static                bit	CCP1M3		@ ((unsigned)&CCP1CON*8)+3;
static volatile       bit	CCP1Y		@ ((unsigned)&CCP1CON*8)+4;
static volatile       bit	CCP1X		@ ((unsigned)&CCP1CON*8)+5;

/* Definitions for RCSTA register */
static volatile       bit	RX9D		@ ((unsigned)&RCSTA*8)+0;
static volatile       bit	OERR		@ ((unsigned)&RCSTA*8)+1;
static volatile       bit	FERR		@ ((unsigned)&RCSTA*8)+2;
static                bit	ADDEN		@ ((unsigned)&RCSTA*8)+3;
static                bit	CREN		@ ((unsigned)&RCSTA*8)+4;
static                bit	SREN		@ ((unsigned)&RCSTA*8)+5;
static                bit	RX9		@ ((unsigned)&RCSTA*8)+6;
static                bit	SPEN		@ ((unsigned)&RCSTA*8)+7;

/* Definitions for CCP2CON register */
static                bit	CCP2M0		@ ((unsigned)&CCP2CON*8)+0;
static                bit	CCP2M1		@ ((unsigned)&CCP2CON*8)+1;
static                bit	CCP2M2		@ ((unsigned)&CCP2CON*8)+2;
static                bit	CCP2M3		@ ((unsigned)&CCP2CON*8)+3;
static volatile       bit	CCP2Y		@ ((unsigned)&CCP2CON*8)+4;
static volatile       bit	CCP2X		@ ((unsigned)&CCP2CON*8)+5;

/* Definitions for ADCON0 register */
static                bit	ADON		@ ((unsigned)&ADCON0*8)+0;
static                bit	CHS3		@ ((unsigned)&ADCON0*8)+1;
static volatile       bit	GODONE		@ ((unsigned)&ADCON0*8)+2;
static                bit	CHS0		@ ((unsigned)&ADCON0*8)+3;
static                bit	CHS1		@ ((unsigned)&ADCON0*8)+4;
static                bit	CHS2		@ ((unsigned)&ADCON0*8)+5;
static                bit	ADCS0		@ ((unsigned)&ADCON0*8)+6;
static                bit	ADCS1		@ ((unsigned)&ADCON0*8)+7;

/* Definitions for OPTION register */
static          bank1 bit	PS0		@ ((unsigned)&OPTION*8)+0;
static          bank1 bit	PS1		@ ((unsigned)&OPTION*8)+1;
static          bank1 bit	PS2		@ ((unsigned)&OPTION*8)+2;
static          bank1 bit	PSA		@ ((unsigned)&OPTION*8)+3;
static          bank1 bit	T0SE		@ ((unsigned)&OPTION*8)+4;
static          bank1 bit	T0CS		@ ((unsigned)&OPTION*8)+5;
static          bank1 bit	INTEDG		@ ((unsigned)&OPTION*8)+6;
static          bank1 bit	RBPU		@ ((unsigned)&OPTION*8)+7;

/* Definitions for TRISA register */
static volatile bank1 bit	TRISA0		@ ((unsigned)&TRISA*8)+0;
static volatile bank1 bit	TRISA1		@ ((unsigned)&TRISA*8)+1;
static volatile bank1 bit	TRISA2		@ ((unsigned)&TRISA*8)+2;
static volatile bank1 bit	TRISA3		@ ((unsigned)&TRISA*8)+3;
static volatile bank1 bit	TRISA4		@ ((unsigned)&TRISA*8)+4;
static volatile bank1 bit	TRISA5		@ ((unsigned)&TRISA*8)+5;
static volatile bank1 bit	TRISA6		@ ((unsigned)&TRISA*8)+6;
static volatile bank1 bit	TRISA7		@ ((unsigned)&TRISA*8)+7;

/* Definitions for TRISB register */
static volatile bank1 bit	TRISB0		@ ((unsigned)&TRISB*8)+0;
static volatile bank1 bit	TRISB1		@ ((unsigned)&TRISB*8)+1;
static volatile bank1 bit	TRISB2		@ ((unsigned)&TRISB*8)+2;
static volatile bank1 bit	TRISB3		@ ((unsigned)&TRISB*8)+3;
static volatile bank1 bit	TRISB4		@ ((unsigned)&TRISB*8)+4;
static volatile bank1 bit	TRISB5		@ ((unsigned)&TRISB*8)+5;
static volatile bank1 bit	TRISB6		@ ((unsigned)&TRISB*8)+6;
static volatile bank1 bit	TRISB7		@ ((unsigned)&TRISB*8)+7;

/* Definitions for TRISC register */
static volatile bank1 bit	TRISC0		@ ((unsigned)&TRISC*8)+0;
static volatile bank1 bit	TRISC1		@ ((unsigned)&TRISC*8)+1;
static volatile bank1 bit	TRISC2		@ ((unsigned)&TRISC*8)+2;
static volatile bank1 bit	TRISC3		@ ((unsigned)&TRISC*8)+3;
static volatile bank1 bit	TRISC4		@ ((unsigned)&TRISC*8)+4;
static volatile bank1 bit	TRISC5		@ ((unsigned)&TRISC*8)+5;
static volatile bank1 bit	TRISC6		@ ((unsigned)&TRISC*8)+6;
static volatile bank1 bit	TRISC7		@ ((unsigned)&TRISC*8)+7;

#if defined(_16F747) || defined(_16F777)
/* Definitions for TRISD register */
static volatile bank1 bit	TRISD0		@ ((unsigned)&TRISD*8)+0;
static volatile bank1 bit	TRISD1		@ ((unsigned)&TRISD*8)+1;
static volatile bank1 bit	TRISD2		@ ((unsigned)&TRISD*8)+2;
static volatile bank1 bit	TRISD3		@ ((unsigned)&TRISD*8)+3;
static volatile bank1 bit	TRISD4		@ ((unsigned)&TRISD*8)+4;
static volatile bank1 bit	TRISD5		@ ((unsigned)&TRISD*8)+5;
static volatile bank1 bit	TRISD6		@ ((unsigned)&TRISD*8)+6;
static volatile bank1 bit	TRISD7		@ ((unsigned)&TRISD*8)+7;

/* Definitions for TRISE register */
static volatile bank1 bit	TRISE0		@ ((unsigned)&TRISE*8)+0;
static volatile bank1 bit	TRISE1		@ ((unsigned)&TRISE*8)+1;
static volatile bank1 bit	TRISE2		@ ((unsigned)&TRISE*8)+2;
static          bank1 bit	PSPMODE		@ ((unsigned)&TRISE*8)+4;
static volatile bank1 bit	IBOV		@ ((unsigned)&TRISE*8)+5;
static volatile bank1 bit	OBF		@ ((unsigned)&TRISE*8)+6;
static volatile bank1 bit	IBF		@ ((unsigned)&TRISE*8)+7;
#endif

/* Definitions for PIE1 register */
static          bank1 bit	TMR1IE		@ ((unsigned)&PIE1*8)+0;
static          bank1 bit	TMR2IE		@ ((unsigned)&PIE1*8)+1;
static          bank1 bit	CCP1IE		@ ((unsigned)&PIE1*8)+2;
static          bank1 bit	SSPIE		@ ((unsigned)&PIE1*8)+3;
static          bank1 bit	TXIE		@ ((unsigned)&PIE1*8)+4;
static          bank1 bit	RCIE		@ ((unsigned)&PIE1*8)+5;
static          bank1 bit	ADIE		@ ((unsigned)&PIE1*8)+6;
#if defined(_16F747) || defined(_16F777)
static          bank1 bit	PSPIE		@ ((unsigned)&PIE1*8)+7;
#endif

/* Definitions for PIE2 register */
static          bank1 bit	CCP2IE		@ ((unsigned)&PIE2*8)+0;
static          bank1 bit	CCP3IE		@ ((unsigned)&PIE2*8)+1;
static          bank1 bit	BCLIE		@ ((unsigned)&PIE2*8)+3;
static          bank1 bit	LVDIE		@ ((unsigned)&PIE2*8)+5;
static          bank1 bit	CMIE		@ ((unsigned)&PIE2*8)+6;
static          bank1 bit	OSFIE		@ ((unsigned)&PIE2*8)+7;

/* Definitions for PCON register */
static volatile bank1 bit	BOR		@ ((unsigned)&PCON*8)+0;
static volatile bank1 bit	POR		@ ((unsigned)&PCON*8)+1;
static          bank1 bit	SBOREN		@ ((unsigned)&PCON*8)+2;

/* Definitions for OSCCON register */
static          bank1 bit	SCS0		@ ((unsigned)&OSCCON*8)+0;
static          bank1 bit	SCS1		@ ((unsigned)&OSCCON*8)+1;
static volatile bank1 bit	IOFS		@ ((unsigned)&OSCCON*8)+2;
static volatile bank1 bit	OSTS		@ ((unsigned)&OSCCON*8)+3;
static          bank1 bit	IRCF0		@ ((unsigned)&OSCCON*8)+4;
static          bank1 bit	IRCF1		@ ((unsigned)&OSCCON*8)+5;
static          bank1 bit	IRCF2		@ ((unsigned)&OSCCON*8)+6;

/* Definitions for OSCTUNE register */
static          bank1 bit	TUN0		@ ((unsigned)&OSCTUNE*8)+0;
static          bank1 bit	TUN1		@ ((unsigned)&OSCTUNE*8)+1;
static          bank1 bit	TUN2		@ ((unsigned)&OSCTUNE*8)+2;
static          bank1 bit	TUN3		@ ((unsigned)&OSCTUNE*8)+3;
static          bank1 bit	TUN4		@ ((unsigned)&OSCTUNE*8)+4;
static          bank1 bit	TUN5		@ ((unsigned)&OSCTUNE*8)+5;

/* Definitions for SSPCON2 register */
static          bank1 bit	SEN		@ ((unsigned)&SSPCON2*8)+0;
static volatile bank1 bit	RSEN		@ ((unsigned)&SSPCON2*8)+1;
static volatile bank1 bit	PEN		@ ((unsigned)&SSPCON2*8)+2;
static volatile bank1 bit	RCEN		@ ((unsigned)&SSPCON2*8)+3;
static volatile bank1 bit	ACKEN		@ ((unsigned)&SSPCON2*8)+4;
static volatile bank1 bit	ACKDT		@ ((unsigned)&SSPCON2*8)+5;
static volatile bank1 bit	ACKSTAT		@ ((unsigned)&SSPCON2*8)+6;
static          bank1 bit	GCEN		@ ((unsigned)&SSPCON2*8)+7;

/* Definitions for SSPSTAT register */
static volatile bank1 bit	BF		@ ((unsigned)&SSPSTAT*8)+0;
static volatile bank1 bit	UA		@ ((unsigned)&SSPSTAT*8)+1;
static volatile bank1 bit	RW		@ ((unsigned)&SSPSTAT*8)+2;
static volatile bank1 bit	START		@ ((unsigned)&SSPSTAT*8)+3;
static volatile bank1 bit	STOP		@ ((unsigned)&SSPSTAT*8)+4;
static volatile bank1 bit	DA		@ ((unsigned)&SSPSTAT*8)+5;
static          bank1 bit	CKE		@ ((unsigned)&SSPSTAT*8)+6;
static          bank1 bit	SMP		@ ((unsigned)&SSPSTAT*8)+7;

/* Definitions for CCP3CON register */
static          bank1 bit	CCP3M0		@ ((unsigned)&CCP3CON*8)+0;
static          bank1 bit	CCP3M1		@ ((unsigned)&CCP3CON*8)+1;
static          bank1 bit	CCP3M2		@ ((unsigned)&CCP3CON*8)+2;
static          bank1 bit	CCP3M3		@ ((unsigned)&CCP3CON*8)+3;
static volatile bank1 bit	CCP3Y		@ ((unsigned)&CCP3CON*8)+4;
static volatile bank1 bit	CCP3X		@ ((unsigned)&CCP3CON*8)+5;

/* Definitions for TXSTA register */
static volatile bank1 bit	TX9D		@ ((unsigned)&TXSTA*8)+0;
static volatile bank1 bit	TRMT		@ ((unsigned)&TXSTA*8)+1;
static          bank1 bit	BRGH		@ ((unsigned)&TXSTA*8)+2;
static          bank1 bit	SYNC		@ ((unsigned)&TXSTA*8)+4;
static          bank1 bit	TXEN		@ ((unsigned)&TXSTA*8)+5;
static          bank1 bit	TX9		@ ((unsigned)&TXSTA*8)+6;
static          bank1 bit	CSRC		@ ((unsigned)&TXSTA*8)+7;

/* Definitions for ADCON2 register */
static          bank1 bit	ACQT0		@ ((unsigned)&ADCON2*8)+2;
static          bank1 bit	ACQT1		@ ((unsigned)&ADCON2*8)+3;
static          bank1 bit	ACQT2		@ ((unsigned)&ADCON2*8)+4;

/* Definitions for CMCON register */
static          bank1 bit	CM0		@ ((unsigned)&CMCON*8)+0;
static          bank1 bit	CM1		@ ((unsigned)&CMCON*8)+1;
static          bank1 bit	CM2		@ ((unsigned)&CMCON*8)+2;
static          bank1 bit	CIS		@ ((unsigned)&CMCON*8)+3;
static          bank1 bit	C1INV		@ ((unsigned)&CMCON*8)+4;
static          bank1 bit	C2INV		@ ((unsigned)&CMCON*8)+5;
static volatile bank1 bit	C1OUT		@ ((unsigned)&CMCON*8)+6;
static volatile bank1 bit	C2OUT		@ ((unsigned)&CMCON*8)+7;

/* Definitions for CVRCON register */
static          bank1 bit	CVR0		@ ((unsigned)&CVRCON*8)+0;
static          bank1 bit	CVR1		@ ((unsigned)&CVRCON*8)+1;
static          bank1 bit	CVR2		@ ((unsigned)&CVRCON*8)+2;
static          bank1 bit	CVR3		@ ((unsigned)&CVRCON*8)+3;
static          bank1 bit	CVRR		@ ((unsigned)&CVRCON*8)+5;
static          bank1 bit	CVROE		@ ((unsigned)&CVRCON*8)+6;
static          bank1 bit	CVREN		@ ((unsigned)&CVRCON*8)+7;

/* Definitions for ADCON1 register */
static          bank1 bit	PCFG0		@ ((unsigned)&ADCON1*8)+0;
static          bank1 bit	PCFG1		@ ((unsigned)&ADCON1*8)+1;
static          bank1 bit	PCFG2		@ ((unsigned)&ADCON1*8)+2;
static          bank1 bit	PCFG3		@ ((unsigned)&ADCON1*8)+3;
static          bank1 bit	VCFG0		@ ((unsigned)&ADCON1*8)+4;
static          bank1 bit	VCFG1		@ ((unsigned)&ADCON1*8)+5;
static          bank1 bit	ADCS2		@ ((unsigned)&ADCON1*8)+6;
static          bank1 bit	ADFM		@ ((unsigned)&ADCON1*8)+7;

/* Definitions for WDTCON register */
static          bank2 bit	SWDTEN		@ ((unsigned)&WDTCON*8)+0;
static          bank2 bit	WDTPS0		@ ((unsigned)&WDTCON*8)+1;
static          bank2 bit	WDTPS1		@ ((unsigned)&WDTCON*8)+2;
static          bank2 bit	WDTPS2		@ ((unsigned)&WDTCON*8)+3;
static          bank2 bit	WDTPS3		@ ((unsigned)&WDTCON*8)+4;

/* Definitions for LVDCON register */
static          bank2 bit	LVDL0		@ ((unsigned)&LVDCON*8)+0;
static          bank2 bit	LVDL1		@ ((unsigned)&LVDCON*8)+1;
static          bank2 bit	LVDL2		@ ((unsigned)&LVDCON*8)+2;
static          bank2 bit	LVDL3		@ ((unsigned)&LVDCON*8)+3;
static          bank2 bit	LVDEN		@ ((unsigned)&LVDCON*8)+4;
static volatile bank2 bit	IRVST		@ ((unsigned)&LVDCON*8)+5;

/* Definitions for EECON1 register */
static volatile bank3 bit	RD		@ ((unsigned)&EECON1*8)+0;

/* define to select flash access routines in pic.h */
#define FLASH_TYPE_R
	

// Configuration Mask Definitions
#define CONFIG_ADDR	0x2007
// Protection of flash memory 
#define PROTECT		0x1FFF
#define UNPROTECT	0x3FFF
// CCP multiplex pin selection 
#define CCPRC1		0x3FFF
#define CCPRB3		0x2FFF
// In-Circuit Debugger Mode 
#define DEBUGEN		0x37FF
#define DEBUGDIS	0x3FFF
// Brown-Out reset enable (combines with BORSEN) 
#define BORV20		0x3FFF
#define BORV27		0x3F7F
#define BORV42		0x3EFF
#define BORV45		0x3E7F
#define BORON		0x3FFF
#define BORDIS		0x3FBF
// Master clear reset pin function
#define MCLREN		0x3FFF
#define MCLRDIS		0x3FDF
// Power up timer enable 
#define PWRTEN		0x3FF7
#define PWRTDIS		0x3FFF
// Watchdog timer enable 
#define WDTEN		0x3FFF
#define WDTDIS		0x3FFB
// Oscillator configurations 
#define RCCLK		0x3FFF
#define RCIO		0x3FFE
#define INTCLK		0x3FFD
#define INTIO		0x3FFC
#define EC		0x3FEF
#define HS		0x3FEE
#define XT		0x3FED
#define LP		0x3FEC
#define CONFIG_ADDR2	0x2008
// Brown-Out reset enable (combines with BOREN) 
#define BORSOFT		0x3FFF
#define BORDISSLEEP	0x3FBF
// Internal External switch over 
#define IESOEN		0x3FFF
#define IESODIS		0x3FFD
// Fail-safe clock monitor 
#define FCMEN		0x3FFF
#define FCMDIS		0x3FFE

#endif
