
#ifndef	_HTC_H_
#warning Header file a8xc5123.h included directly. Use #include <htc.h> instead.
#endif


 /* header file for the Atmel microcontrollers
	AT83C5123
	AT83EB5123
 */

#ifndef	__A8XC5123_H

#define	__A8XC5123_H

typedef struct {
	unsigned B7:1; //This is the most signifigant bit
	unsigned B6:1;
	unsigned B5:1;
	unsigned B4:1;
	unsigned B3:1;
	unsigned B2:1;
	unsigned B1:1;
	unsigned B0:1;
}	SFR_BITS;

/* note some addresses contain 2 SFRs. In this case, one SFR
 * maps to an upper, and the other to a lower cell at that
 * address. Cell selection is done via the SCRS bit in the 
 * SCSR register.
 * SCRS = 0 selects the upper cell.
 * SCRS = 1 selects the lower cell. */

//Special Function Registers
static volatile unsigned char SP	@ 0x81;
static volatile unsigned char DPL	@ 0x82;
static volatile unsigned char DPH	@ 0x83;
// 16-Bit definition
static		unsigned char CKSEL	@ 0x85;
static volatile unsigned char PCON	@ 0x87;
static volatile unsigned char TCON	@ 0x88;
static          unsigned char TMOD	@ 0x89;
static volatile unsigned char TL0	@ 0x8A;
static volatile unsigned char TL1	@ 0x8B;
static volatile unsigned char TH0	@ 0x8C;
static volatile unsigned char TH1	@ 0x8D;
static		unsigned char CKCON0	@ 0x8F;
static volatile unsigned char P1	@ 0x90;
static volatile unsigned char PMOD0	@ 0x91;
static		unsigned char CKRL	@ 0x97;
static volatile unsigned char SCON	@ 0x98;
static volatile unsigned char SBUF	@ 0x99;
static		unsigned char BRL	@ 0x9A;
static		unsigned char BDRCON	@ 0x9B;
static		unsigned char ISEL	@ 0xA1;
static volatile unsigned char PLLCON	@ 0xA3;
static		unsigned char PLLDIV	@ 0xA4;
static		unsigned char WDTRST	@ 0xA6;
static		unsigned char WDTPRG	@ 0xA7;
static          unsigned char IEN0	@ 0xA8;
static          unsigned char SADDR	@ 0xA9;
static volatile unsigned char SCTBUF	@ 0xAA;
// lower cell register mapped to same address
static volatile unsigned char SCRBUF	@ 0xAA;
static		unsigned char SCSR	@ 0xAB;
static volatile unsigned char SCCON	@ 0xAC;
// lower cell register mapped to same address
static volatile unsigned char SCETU0	@ 0xAC;
static volatile unsigned char SCISR	@ 0xAD;
// lower cell register mapped to same address
static volatile unsigned char SCETU1	@ 0xAD;
static volatile unsigned char SCIIR	@ 0xAE;
// lower cell register mapped to same address
static volatile unsigned char SCIER	@ 0xAE;
static volatile unsigned char CKCON1	@ 0xAF;
static volatile unsigned char P3	@ 0xB0;
static          unsigned char IEN1	@ 0xB1;
static          unsigned char IPL1	@ 0xB2;
static          unsigned char IPH1	@ 0xB3;
static		unsigned char SCWT0	@ 0xB4;
// lower cell register mapped to same address
static		unsigned char SCGT0	@ 0xB4;
static		unsigned char SCWT1	@ 0xB5;
// lower cell register mapped to same address
static		unsigned char SCGT1	@ 0xB5;
static		unsigned char SCWT2	@ 0xB6;
// lower cell register mapped to same address
static volatile unsigned char SCICR	@ 0xB6;
static          unsigned char IPH0	@ 0xB7;
static          unsigned char IPL0	@ 0xB8;
static          unsigned char SADEN	@ 0xB9;
static volatile unsigned char UFNUML	@ 0xBA;
static volatile unsigned char UFNUMH	@ 0xBB;
static volatile unsigned char USBCON	@ 0xBC;
static volatile unsigned char USBINT	@ 0xBD;
static		unsigned char USBIEN	@ 0xBE;
static		unsigned char DCCKPS	@ 0xBF;
static volatile unsigned char P4	@ 0xC0;
// lower cell register mapped to same address
static		unsigned char SCICLK	@ 0xC1;
// Alternate definition
static		unsigned char SCCCLK	@ 0xC1;
static		unsigned char UEPIEN	@ 0xC2;
static volatile unsigned char USBADDR	@ 0xC6;
static		unsigned char UEPNUM	@ 0xC7;
static volatile unsigned char UEPSTAX	@ 0xCE;
static volatile unsigned char UEPDATX	@ 0xCF;
static volatile unsigned char PSW	@ 0xD0;
static volatile unsigned char UEPCONX	@ 0xD4;
static		unsigned char UEPRST	@ 0xD5;
static volatile unsigned char ACC	@ 0xE0;
static volatile unsigned char UBYCTX	@ 0xE2;
static volatile unsigned char P5	@ 0xE8;
static volatile unsigned char B		@ 0xF0;
static volatile unsigned char UEPINT	@ 0xF8;

static		SFR_BITS	 CKSEL_BITS	@ 0x85;
static volatile SFR_BITS	 PCON_BITS	@ 0x87;
static volatile SFR_BITS	 TCON_BITS	@ 0x88;
static          SFR_BITS	 TMOD_BITS	@ 0x89;
static		SFR_BITS	 CKCON0_BITS	@ 0x8F;
static volatile SFR_BITS	 P1_BITS	@ 0x90;
static volatile SFR_BITS	 PMOD0_BITS	@ 0x91;
static volatile SFR_BITS	 SCON_BITS	@ 0x98;
static		SFR_BITS	 BDRCON_BITS	@ 0x9B;
static		SFR_BITS	 ISEL_BITS	@ 0xA1;
static volatile SFR_BITS	 PLLCON_BITS	@ 0xA3;
static		SFR_BITS	 WDTPRG_BITS	@ 0xA7;
static          SFR_BITS	 IEN0_BITS	@ 0xA8;
static          SFR_BITS	 SADDR_BITS	@ 0xA9;
static		SFR_BITS	 SCSR_BITS	@ 0xAB;
static volatile SFR_BITS	 SCCON_BITS	@ 0xAC;
// lower cell register mapped to same address
static volatile SFR_BITS	 SCETU0_BITS	@ 0xAC;
static volatile SFR_BITS	 SCISR_BITS	@ 0xAD;
// lower cell register mapped to same address
static volatile SFR_BITS	 SCETU1_BITS	@ 0xAD;
static volatile SFR_BITS	 SCIIR_BITS	@ 0xAE;
// lower cell register mapped to same address
static volatile SFR_BITS	 SCIER_BITS	@ 0xAE;
static volatile SFR_BITS	 CKCON1_BITS	@ 0xAF;
static volatile SFR_BITS	 P3_BITS	@ 0xB0;
static          SFR_BITS	 IEN1_BITS	@ 0xB1;
static          SFR_BITS	 IPL1_BITS	@ 0xB2;
static          SFR_BITS	 IPH1_BITS	@ 0xB3;
// lower cell register mapped to same address
static volatile SFR_BITS	 SCICR_BITS	@ 0xB6;
static          SFR_BITS	 IPH0_BITS	@ 0xB7;
static          SFR_BITS	 IPL0_BITS	@ 0xB8;
static          SFR_BITS	 SADEN_BITS	@ 0xB9;
static volatile SFR_BITS	 USBCON_BITS	@ 0xBC;
static volatile SFR_BITS	 USBINT_BITS	@ 0xBD;
static		SFR_BITS	 USBIEN_BITS	@ 0xBE;
static		SFR_BITS	 DCCKPS_BITS	@ 0xBF;
static volatile SFR_BITS	 P4_BITS	@ 0xC0;
static		SFR_BITS	 UEPIEN_BITS	@ 0xC2;
static volatile SFR_BITS	 UEPSTAX_BITS	@ 0xCE;
static volatile SFR_BITS	 PSW_BITS	@ 0xD0;
static volatile SFR_BITS	 UEPCONX_BITS	@ 0xD4;
static		SFR_BITS	 UEPRST_BITS	@ 0xD5;
static volatile SFR_BITS	 ACC_BITS	@ 0xE0;
static volatile SFR_BITS	 P5_BITS	@ 0xE8;
static volatile SFR_BITS	 B_BITS		@ 0xF0;
static volatile SFR_BITS	 UEPINT_BITS	@ 0xF8;


// Bit Addressable Locations
// Timer Control TCON
static 		bit	IT0	@ 0x88;
static volatile bit	IE0	@ 0x89;
static 		bit	IT1	@ 0x8A;
static volatile bit	IE1	@ 0x8B;
static 		bit	TR0	@ 0x8C;
static volatile bit	TF0	@ 0x8D;
static 		bit	TR1	@ 0x8E;
static volatile bit	TF1	@ 0x8F;

// Port 1 P1
static volatile bit	P10	@ 0x90;
static volatile bit	P11	@ 0x91;
static volatile bit	P12	@ 0x92;
static volatile bit	P13	@ 0x93;
static volatile bit	P14	@ 0x94;
static volatile bit	P15	@ 0x95;
static volatile bit	P16	@ 0x96;
static volatile bit	P17	@ 0x97;
// Alternate functions
static volatile bit	CIO	@ 0x90;
static volatile bit	CC8	@ 0x91;
static volatile bit	CPRES	@ 0x92;
static volatile bit	CC4	@ 0x93;
static volatile bit	CCLK	@ 0x94;
static volatile bit	CRST	@ 0x95;
static volatile bit	CCLK1	@ 0x97;

// Serial Control SCON
static volatile bit	RI	@ 0x98;
static volatile bit	TI	@ 0x99;
static volatile bit	RB8	@ 0x9A;
static		bit	TB8	@ 0x9B;
static 		bit	REN	@ 0x9C;
static		bit	SM2	@ 0x9D;
static		bit	SM1	@ 0x9E;
static volatile bit	SM0	@ 0x9F;
// alternate function
static volatile bit	FE	@ 0x9F;

// Interrupt Enable 0 IEN0
static 		bit 	EX0 	@ 0xA8;
static 		bit 	ET0 	@ 0xA9;
static 		bit 	EX1 	@ 0xAA;
static 		bit 	ET1 	@ 0xAB;
static 		bit 	ES 	@ 0xAC;
static 		bit 	EA	@ 0xAF;

// Port 3 P3
static volatile bit	P30	@ 0xB0;
static volatile bit	P31	@ 0xB1;
static volatile bit	P32	@ 0xB2;
static volatile bit	P33	@ 0xB3;
static volatile bit	P34	@ 0xB4;
static volatile bit	P35	@ 0xB5;
static volatile bit	P36	@ 0xB6;
static volatile bit	P37	@ 0xB7;
// Alternate Functions
static volatile bit	RXD	@ 0xB0;
static volatile bit	TXD	@ 0xB1;
static volatile bit	INT0	@ 0xB2;
static volatile bit	INT1	@ 0xB3;
static volatile bit	T0	@ 0xB4;
static volatile bit	T1	@ 0xB5;
static volatile bit	LED0	@ 0xB2;
static volatile bit	LED1	@ 0xB4;
static volatile bit	LED2	@ 0xB6;
static volatile bit	LED3	@ 0xB7;

// definitions for register IPL0
static 		bit 	PX0L 	@ 0xB8;
static 		bit 	PT0L 	@ 0xB9;
static 		bit 	PX1L 	@ 0xBA;
static 		bit 	PT1L 	@ 0xBB;
static 		bit 	PSL 	@ 0xBC;
// alternate definitions
static 		bit 	PX0 	@ 0xB8;
static 		bit 	PT0 	@ 0xB9;
static 		bit 	PX1 	@ 0xBA;
static 		bit 	PT1 	@ 0xBB;
static 		bit 	PS 	@ 0xBC;

// Port 4
static volatile bit	P46	@ 0xC6;
static volatile bit	P47	@ 0xC7;

// Program Status Word PSW
static volatile bit	P	@ 0xD0;
static volatile bit	F1	@ 0xD1;
static volatile bit	OV	@ 0xD2;
static 		bit	RS0	@ 0xD3;
static 		bit	RS1	@ 0xD4;
static volatile bit	F0	@ 0xD5;
static volatile bit	AC	@ 0xD6;
static volatile bit	CY	@ 0xD7;

// Accumulator ACC
static volatile bit	ACC0	@ 0xE0;
static volatile bit	ACC1	@ 0xE1;
static volatile bit	ACC2	@ 0xE2;
static volatile bit	ACC3	@ 0xE3;
static volatile bit	ACC4	@ 0xE4;
static volatile bit	ACC5	@ 0xE5;
static volatile bit	ACC6	@ 0xE6;
static volatile bit	ACC7	@ 0xE7;

// Port 5 P5
static volatile bit	P50	@ 0xE8;
static volatile bit	P51	@ 0xE9;
static volatile bit	P52	@ 0xEA;
// Alternate function
static volatile bit	PLLF	@ 0xEA;

// B register
static volatile bit	B0	@ 0xF0;
static volatile bit	B1	@ 0xF1;
static volatile bit	B2	@ 0xF2;
static volatile bit	B3	@ 0xF3;
static volatile bit	B4	@ 0xF4;
static volatile bit	B5	@ 0xF5;
static volatile bit	B6	@ 0xF6;
static volatile bit	B7	@ 0xF7;

// definitions for register UEPINT
static volatile bit	EP0INT	@ 0xF8;
static volatile bit	EP1INT	@ 0xF9;
static volatile bit	EP2INT	@ 0xFA;
static volatile bit	EP3INT	@ 0xFB;


// Interrupt Vectors
#define	RESET	0
#define	EXTINT0	0x03
#define TIMER0	0x0B
#define	EXTINT1	0x13
#define	TIMER1	0x1B
#define	SERIAL	0x23

#endif
