
#ifndef	_HTC_H_
#warning Header file 9xc8132.h included directly. Use #include <htc.h> instead.
#endif


 /* header file for the Hynix microcontrollers
	HMS91C8108
	HMS91C8116
	HMS91C8132
	HMS97C8132
 */

#ifndef	__9XC8132_H

#define	__9XC8132_H

typedef struct {
	unsigned B7:1; //This is the most signifigant bit
	unsigned B6:1;
	unsigned B5:1;
	unsigned B4:1;
	unsigned B3:1;
	unsigned B2:1;
	unsigned B1:1;
	unsigned B0:1;
}	SFR_BITS;

//Special Function Registers
static		unsigned char SCMOD	@ 0x80;
static volatile unsigned char SP	@ 0x81;
static volatile unsigned char DPL	@ 0x82;
static volatile unsigned char DPH	@ 0x83;
// 16 bit definition
static volatile unsigned char ADCCON	@ 0x84;
static volatile unsigned char ADCDR	@ 0x85;
static volatile unsigned char PLLDEBUG	@ 0x86;
static volatile unsigned char PCON	@ 0x87;
// bank 0 register
static volatile unsigned char TCON	@ 0x88;
// bank 1 register
static volatile unsigned char P0DATA	@ 0x88;
static          unsigned char TMOD	@ 0x89;
static volatile unsigned char TL0	@ 0x8A;
static volatile unsigned char TL1	@ 0x8B;
static volatile unsigned char TH0	@ 0x8C;
static volatile unsigned char TH1	@ 0x8D;
static volatile unsigned char T34CON	@ 0x90;
static		unsigned char T34MOD	@ 0x91;
static volatile unsigned char TL3	@ 0x92;
static volatile unsigned char TL4	@ 0x93;
static volatile unsigned char TH3	@ 0x94;
static volatile unsigned char TH4	@ 0x95;
static volatile unsigned char TL5	@ 0x96;
static volatile unsigned char TH5	@ 0x97;
// bank 0 register
static volatile unsigned char SCON	@ 0x98;
// bank 1 register
static volatile unsigned char P1DATA	@ 0x98;
static volatile unsigned char SBUF	@ 0x99;
static volatile unsigned char T5CON	@ 0x9D;
static		unsigned char T5INITL	@ 0x9E;
static		unsigned char T5INITH	@ 0x9F;
static		unsigned char S12CON	@ 0xA0;
static volatile unsigned char SBUF1	@ 0xA1;
static volatile unsigned char SBUF2	@ 0xA2;
static		unsigned char P0CON	@ 0xA4;
static		unsigned char P1CON	@ 0xA5;
static		unsigned char P2CON	@ 0xA6;
static		unsigned char P3CON	@ 0xA7;
// bank 0 register
static          unsigned char IE	@ 0xA8;
// bank 1 register
static volatile unsigned char P2DATA	@ 0xA8;
static		unsigned char P4CON	@ 0xAC;
static		unsigned char P5CON	@ 0xAD;
static		unsigned char P6CON	@ 0xAE;
static		unsigned char P7CON	@ 0xAF;
static		unsigned char IE2	@ 0xB0;
static		unsigned char IP2	@ 0xB1;
static		unsigned char P0MOD	@ 0xB4;
static		unsigned char P1MOD	@ 0xB5;
static		unsigned char P2MOD	@ 0xB6;
static		unsigned char P3MOD	@ 0xB7;
// bank 0 register
static		unsigned char IP	@ 0xB8;
// bank 1 register
static volatile unsigned char P3DATA	@ 0xB8;
static		unsigned char P4MOD	@ 0xBC;
static		unsigned char P5MOD	@ 0xBD;
static		unsigned char P6MOD	@ 0xBE;
static		unsigned char P7MOD	@ 0xBF;
static		unsigned char IE3	@ 0xC0;
static		unsigned char IP3	@ 0xC1;
static		unsigned char PSLOPE	@ 0xC7;
// bank 0 register
static volatile unsigned char T2CON	@ 0xC8;
// bank 1 register
static volatile unsigned char P4DATA	@ 0xC8;
static volatile unsigned char RCAP2L	@ 0xCA;
static volatile unsigned char RCAP2H	@ 0xCB;
static volatile unsigned char TL2	@ 0xCC;
static volatile unsigned char TH2	@ 0xCD;
static volatile unsigned char PSW	@ 0xD0;
static volatile unsigned char PFDCR	@ 0xD6;
static		unsigned char CPUMD	@ 0xD7;
// bank 0 register
static volatile unsigned char IR2	@ 0xD8;
// bank 1 register
static volatile unsigned char P5DATA	@ 0xD8;
static		unsigned char IT2	@ 0xD9;
static volatile unsigned char ACC	@ 0xE0;
// bank 0 register
static volatile unsigned char IR3	@ 0xE8;
// bank 1 register
static volatile unsigned char P6DATA	@ 0xE8;
static		unsigned char AMINC	@ 0xEB;
static		unsigned char FMINC	@ 0xEC;
static		unsigned char AMPLNC	@ 0xED;
static		unsigned char AMPHNC	@ 0xEE;
static		unsigned char FMPNC	@ 0xEF;
static volatile unsigned char B		@ 0xF0;
static volatile unsigned char PLLMOD	@ 0xF1;
static		unsigned char PLLDRH	@ 0xF2;
static		unsigned char PLLDRL	@ 0xF3;
static volatile unsigned char IFCMOD	@ 0xF4;
static volatile unsigned char IFCDR2	@ 0xF5;
static volatile unsigned char IFCDR1	@ 0xF6;
static volatile unsigned char IFCDR0	@ 0xF7;
// bank 0 register
static volatile unsigned char WDTCON	@ 0xF8;
// bank 1 register
static volatile unsigned char P7DATA	@ 0xF8;
static volatile unsigned char WDTDR	@ 0xF9;
static		unsigned char RDPG	@ 0xFC;
static		unsigned char WRPG	@ 0xFD;
static		unsigned char SFRPG	@ 0xFF;

static		SFR_BITS	 SCMOD_BITS	@ 0x80;
static volatile SFR_BITS	 ADCCON_BITS	@ 0x84;
static volatile SFR_BITS	 PLLDEBUG_BITS	@ 0x86;
static volatile SFR_BITS	 PCON_BITS	@ 0x87;
// bank 0 register
static volatile SFR_BITS	 TCON_BITS	@ 0x88;
// bank 1 register
static volatile SFR_BITS	 P0DATA_BITS	@ 0x88;
static          SFR_BITS	 TMOD_BITS	@ 0x89;
static volatile SFR_BITS	 T34CON_BITS	@ 0x90;
static		SFR_BITS	 T34MOD_BITS	@ 0x91;
// bank 0 register
static volatile SFR_BITS	 SCON_BITS	@ 0x98;
// bank 1 register
static volatile SFR_BITS	 P1DATA_BITS	@ 0x98;
static volatile SFR_BITS	 T5CON_BITS	@ 0x9D;
static		SFR_BITS	 S12CON_BITS	@ 0xA0;
static volatile SFR_BITS	 SBUF2_BITS	@ 0xA2;
static		SFR_BITS	 P0CON_BITS	@ 0xA4;
static		SFR_BITS	 P1CON_BITS	@ 0xA5;
static		SFR_BITS	 P2CON_BITS	@ 0xA6;
static		SFR_BITS	 P3CON_BITS	@ 0xA7;
// bank 0 register
static          SFR_BITS	 IE_BITS	@ 0xA8;
// bank 1 register
static volatile SFR_BITS	 P2DATA_BITS	@ 0xA8;
static		SFR_BITS	 P4CON_BITS	@ 0xAC;
static		SFR_BITS	 P5CON_BITS	@ 0xAD;
static		SFR_BITS	 P6CON_BITS	@ 0xAE;
static		SFR_BITS	 P7CON_BITS	@ 0xAF;
static		SFR_BITS	 IE2_BITS	@ 0xB0;
static		SFR_BITS	 IP2_BITS	@ 0xB1;
static		SFR_BITS	 P0MOD_BITS	@ 0xB4;
static		SFR_BITS	 P1MOD_BITS	@ 0xB5;
static		SFR_BITS	 P2MOD_BITS	@ 0xB6;
static		SFR_BITS	 P3MOD_BITS	@ 0xB7;
// bank 0 register
static          SFR_BITS	 IP_BITS	@ 0xB8;
// bank 1 register
static volatile SFR_BITS	 P3DATA_BITS	@ 0xB8;
static		SFR_BITS	 P4MOD_BITS	@ 0xBC;
static		SFR_BITS	 P5MOD_BITS	@ 0xBD;
static		SFR_BITS	 P6MOD_BITS	@ 0xBE;
static		SFR_BITS	 P7MOD_BITS	@ 0xBF;
static		SFR_BITS	 IE3_BITS	@ 0xC0;
static		SFR_BITS	 IP3_BITS	@ 0xC1;
// bank 0 register
static volatile SFR_BITS	 T2CON_BITS	@ 0xC8;
// bank 1 register
static volatile SFR_BITS	 P4DATA_BITS	@ 0xC8;
static volatile SFR_BITS	 PSW_BITS	@ 0xD0;
static volatile SFR_BITS	 PFDCR_BITS	@ 0xD6;
static		SFR_BITS	 CPUMD_BITS	@ 0xD7;
// bank 0 register
static volatile SFR_BITS	 IR2_BITS	@ 0xD8;
// bank 1 register
static volatile SFR_BITS	 P5DATA_BITS	@ 0xD8;
static		SFR_BITS	 IT2_BITS	@ 0xD9;
static volatile SFR_BITS	 ACC_BITS	@ 0xE0;
// bank 0 register
static volatile SFR_BITS	 IR3_BITS	@ 0xE8;
// bank 1 register
static volatile SFR_BITS	 P6DATA_BITS	@ 0xE8;
static		SFR_BITS	 AMINC_BITS	@ 0xEB;
static		SFR_BITS	 FMINC_BITS	@ 0xEC;
static		SFR_BITS	 AMPLNC_BITS	@ 0xED;
static		SFR_BITS	 AMPHNC_BITS	@ 0xEE;
static		SFR_BITS	 FMPNC_BITS	@ 0xEF;
static volatile SFR_BITS	 B_BITS		@ 0xF0;
static volatile SFR_BITS	 PLLMOD_BITS	@ 0xF1;
static volatile SFR_BITS	 IFCMOD_BITS	@ 0xF4;
static volatile SFR_BITS	 IFCDR2_BITS	@ 0xF5;
static volatile SFR_BITS	 IFCDR1_BITS	@ 0xF6;
static volatile SFR_BITS	 IFCDR0_BITS	@ 0xF7;
// bank 0 register
static volatile SFR_BITS	 WDTCON_BITS	@ 0xF8;
// bank 1 register
static volatile SFR_BITS	 P7DATA_BITS	@ 0xF8;
static		SFR_BITS	 RDPG_BITS	@ 0xFC;
static		SFR_BITS	 WRPG_BITS	@ 0xFD;
static		SFR_BITS	 SFRPG_BITS	@ 0xFF;


// Bit Addressable Locations
// definitions for register SCMOD
static 		bit	SCMOD0	@ 0x80;
static 		bit	SCMOD1	@ 0x81;
static 		bit	SCMOD2	@ 0x82;
static 		bit	SCSW	@ 0x83;
static 		bit	SCSTOP	@ 0x84;

// definitions for register P0DATA
static volatile bit	P0DATA0	@ 0x88;
static volatile bit	P0DATA1	@ 0x89;
static volatile bit	P0DATA2	@ 0x8A;
static volatile bit	P0DATA3	@ 0x8B;
static volatile bit	P0DATA4	@ 0x8C;
static volatile bit	P0DATA5	@ 0x8D;
static volatile bit	P0DATA6	@ 0x8E;
static volatile bit	P0DATA7	@ 0x8F;

//Timer Control TCON
static 		bit	IT0	@ 0x88;
static volatile bit	IE0	@ 0x89;
static 		bit	IT1	@ 0x8A;
static volatile bit	IE1	@ 0x8B;
static 		bit	TR0	@ 0x8C;
static volatile bit	TF0	@ 0x8D;
static 		bit	TR1	@ 0x8E;
static volatile bit	TF1	@ 0x8F;

// definitions for register T34CON
static		bit	T4_SUB	@ 0x90;
static		bit	T3_SUB	@ 0x92;
static		bit	TR3	@ 0x94;
static volatile bit	TF3	@ 0x95;
static		bit	TR4	@ 0x96;
static volatile bit	TF4	@ 0x97;

// definitions for register P1DATA
static volatile bit	P1DATA0	@ 0x98;
static volatile bit	P1DATA1	@ 0x99;
static volatile bit	P1DATA2	@ 0x9A;
static volatile bit	P1DATA3	@ 0x9B;
static volatile bit	P1DATA4	@ 0x9C;
static volatile bit	P1DATA5	@ 0x9D;
static volatile bit	P1DATA6	@ 0x9E;
static volatile bit	P1DATA7	@ 0x9F;

//Serial Control SCON
static volatile bit	RI	@ 0x98;
static volatile bit	TI	@ 0x99;
static volatile bit	RB8	@ 0x9A;
static		bit	TB8	@ 0x9B;
static 		bit	REN	@ 0x9C;
static		bit	SM2	@ 0x9D;
static		bit	SM1	@ 0x9E;
static volatile bit	SM0	@ 0x9F;

// Serial port 1/2 control register S12CON
static		bit	SIO1CK0	@ 0xA0;
static		bit	SIO1CK1	@ 0xA1;
static		bit	SIO1HIZ	@ 0xA2;
static		bit	SIO1TS	@ 0xA3;
static		bit	SIO2CK0	@ 0xA4;
static		bit	SIO2CK1	@ 0xA5;
static		bit	SIO2HIZ	@ 0xA6;
static		bit	SIO2TS	@ 0xA7;

//Interrupt Enable IE
static		bit	IEX0	@ 0xA8;
static		bit	IET0	@ 0xA9;
static		bit	IEX1	@ 0xAA;
static		bit	IET1	@ 0xAB;
static 		bit	IES0	@ 0xAC;
static		bit	IET2	@ 0xAD;
static 		bit	EA	@ 0xAF;

// definitions for register P2DATA
static volatile bit	P2DATA0	@ 0xA8;
static volatile bit	P2DATA1	@ 0xA9;
static volatile bit	P2DATA2	@ 0xAA;
static volatile bit	P2DATA3	@ 0xAB;
static volatile bit	P2DATA4	@ 0xAC;
static volatile bit	P2DATA5	@ 0xAD;
static volatile bit	P2DATA6	@ 0xAE;
static volatile bit	P2DATA7	@ 0xAF;

// Interrupt enable register 2 IE2
static		bit	IEX2	@ 0xB0;
static		bit	IEX3	@ 0xB1;
static		bit	IEX4	@ 0xB2;
static		bit	IEX5	@ 0xB3;
static		bit	IEX6	@ 0xB4;

// Interrupt Priority
static 		bit	IPX0	@ 0xB8;
static 		bit	IPT0	@ 0xB9;
static 		bit	IPX1	@ 0xBA;
static 		bit	IPT1	@ 0xBB;
static 		bit	IPS0	@ 0xBC;
static 		bit	IPT2	@ 0xBD;

// definitions for register P3DATA
static volatile bit	P3DATA0	@ 0xB8;
static volatile bit	P3DATA1	@ 0xB9;
static volatile bit	P3DATA2	@ 0xBA;
static volatile bit	P3DATA3	@ 0xBB;
static volatile bit	P3DATA4	@ 0xBC;
static volatile bit	P3DATA5	@ 0xBD;
static volatile bit	P3DATA6	@ 0xBE;
static volatile bit	P3DATA7	@ 0xBF;

// Interrupt enable register 3 IE3
static		bit	IET3	@ 0xC0;
static		bit	IET4	@ 0xC1;
static		bit	IES1	@ 0xC2;
static		bit	IES2	@ 0xC3;
static		bit	IEIF	@ 0xC4;
static		bit	IEADC	@ 0xC5;
static		bit	IEWDT	@ 0xC6;

// definitions for register P4DATA
static volatile bit	P4DATA0	@ 0xC8;
static volatile bit	P4DATA1	@ 0xC9;
static volatile bit	P4DATA2	@ 0xCA;
static volatile bit	P4DATA3	@ 0xCB;
static volatile bit	P4DATA4	@ 0xCC;
static volatile bit	P4DATA5	@ 0xCD;
static volatile bit	P4DATA6	@ 0xCE;
static volatile bit	P4DATA7	@ 0xCF;

//Timer 2 Control T2CON
static 		bit	CPRL2	@ 0xC8;
static 		bit	CT2	@ 0xC9;
static 		bit	TR2	@ 0xCA;
static 		bit	EXEN2	@ 0xCB;
static		bit	TCLK	@ 0xCC;
static		bit	RCLK	@ 0xCD;
static volatile	bit	EXF2	@ 0xCE;
static volatile	bit	TF2	@ 0xCF;

//Program Status Word PSW
static volatile bit	P	@ 0xD0;
static volatile bit	OV	@ 0xD2;
static 		bit	RS0	@ 0xD3;
static 		bit	RS1	@ 0xD4;
static volatile bit	F0	@ 0xD5;
static volatile bit	AC	@ 0xD6;
static volatile bit	CY	@ 0xD7;

// Interrupt request register 2 IR2
static volatile bit	IRX2	@ 0xD8;
static volatile bit	IRX3	@ 0xD9;
static volatile bit	IRX4	@ 0xDA;
static volatile bit	IRX5	@ 0xDB;
static volatile bit	IRX6	@ 0xDC;

// definitions for register P5DATA
static volatile bit	P5DATA0	@ 0xD8;
static volatile bit	P5DATA1	@ 0xD9;
static volatile bit	P5DATA2	@ 0xDA;
static volatile bit	P5DATA3	@ 0xDB;
static volatile bit	P5DATA4	@ 0xDC;
static volatile bit	P5DATA5	@ 0xDD;
static volatile bit	P5DATA6	@ 0xDE;
static volatile bit	P5DATA7	@ 0xDF;

//Accumulator ACC
static volatile bit	ACC0	@ 0xE0;
static volatile bit	ACC1	@ 0xE1;
static volatile bit	ACC2	@ 0xE2;
static volatile bit	ACC3	@ 0xE3;
static volatile bit	ACC4	@ 0xE4;
static volatile bit	ACC5	@ 0xE5;
static volatile bit	ACC6	@ 0xE6;
static volatile bit	ACC7	@ 0xE7;

// Interrupt request register 3 IR3
static volatile bit	IRT3	@ 0xE8;
static volatile bit	IRT4	@ 0xE9;
static volatile bit	IRS1	@ 0xEA;
static volatile bit	IRS2	@ 0xEB;
static volatile bit	IRIFC	@ 0xEC;
static volatile bit	IRADC	@ 0xED;
static volatile bit	IRWDT	@ 0xEE;

// definitions for register P6DATA
static volatile bit	P6DATA0	@ 0xE8;
static volatile bit	P6DATA1	@ 0xE9;
static volatile bit	P6DATA2	@ 0xEA;
static volatile bit	P6DATA3	@ 0xEB;
static volatile bit	P6DATA4	@ 0xEC;
static volatile bit	P6DATA5	@ 0xED;
static volatile bit	P6DATA6	@ 0xEE;
static volatile bit	P6DATA7	@ 0xEF;

//B register
static volatile bit	B0	@ 0xF0;
static volatile bit	B1	@ 0xF1;
static volatile bit	B2	@ 0xF2;
static volatile bit	B3	@ 0xF3;
static volatile bit	B4	@ 0xF4;
static volatile bit	B5	@ 0xF5;
static volatile bit	B6	@ 0xF6;
static volatile bit	B7	@ 0xF7;

// definitions for register P7DATA
static volatile bit	P7DATA0	@ 0xF8;
static volatile bit	P7DATA1	@ 0xF9;
static volatile bit	P7DATA2	@ 0xFA;
static volatile bit	P7DATA3	@ 0xFB;
static volatile bit	P7DATA4	@ 0xFC;
static volatile bit	P7DATA5	@ 0xFD;
static volatile bit	P7DATA6	@ 0xFE;
static volatile bit	P7DATA7	@ 0xFF;

// Beeper & watchdog control register WDTCON
static		bit	WDTMD0	@ 0xF8;
static		bit	WDTMD1	@ 0xF9;
static		bit	WDTMD2	@ 0xFA;
static		bit	WDTMK	@ 0xFB;
static volatile bit	RUNWDT	@ 0xFC;
static		bit	BEEPMD0	@ 0xFD;
static		bit	BEEPMD1	@ 0xFE;
static		bit	RUNBEEP	@ 0xFF;


//Interrupt Vectors
#define	RESET	0
#define	EXTINT0	0x03
#define TIMER0	0x0B
#define	EXTINT1	0x13
#define	TIMER1	0x1B
#define	SERIAL	0x23
#define	TIMER2	0x2B
#define	INTWDT	0x33
#define	INTIFC	0x3B
#define	INTAD	0x43
#define	EXTINT2	0x4B
#define	EXTINT3	0x53
#define	EXTINT4	0x5B
#define	SERIAL1	0x63
#define	SERIAL2	0x6B
#define	EXTINT5	0x73
#define	EXTINT6	0x7B
#define	TIMER3	0x83
#define	TIMER45	0x8B

#endif
