
#ifndef	_HTC_H_
#warning Header file pic16f636.h included directly. Use #include <htc.h> instead.
#endif


 /* header file for the MICROCHIP PIC microcontrollers
  * PIC12F635
  * PIC16F636
  * PIC16F639
 */

#ifndef	__PIC16F636_H
#define	__PIC16F636_H

// Special function register definitions

static volatile       unsigned char	TMR0		@ 0x01;
static volatile       unsigned char	PCL		@ 0x02;
static volatile       unsigned char	STATUS		@ 0x03;
static                unsigned char	FSR		@ 0x04;
#if defined(_16F636) || defined(_16F639)
static volatile       unsigned char	PORTA		@ 0x05;
static volatile       unsigned char	PORTC		@ 0x07;
#else
static volatile       unsigned char	GPIO		@ 0x05;
#endif
static volatile       unsigned char	PCLATH		@ 0x0A;
static volatile       unsigned char	INTCON		@ 0x0B;
static volatile       unsigned char	PIR1		@ 0x0C;
static volatile       unsigned char	TMR1L		@ 0x0E;
static volatile       unsigned char	TMR1H		@ 0x0F;
static volatile       unsigned char	T1CON		@ 0x10;
static volatile       unsigned char	WDTCON		@ 0x18;
static volatile       unsigned char	CMCON0		@ 0x19;
static                unsigned char	CMCON1		@ 0x1A;
static          bank1 unsigned char	OPTION		@ 0x81;
#if defined(_16F636) || defined(_16F639)
static volatile bank1 unsigned char	TRISA		@ 0x85;
static volatile bank1 unsigned char	TRISC		@ 0x87;
#else
static volatile bank1 unsigned char	TRISIO		@ 0x85;
#endif
static          bank1 unsigned char	PIE1		@ 0x8C;
static volatile bank1 unsigned char	PCON		@ 0x8E;
static volatile bank1 unsigned char	OSCCON		@ 0x8F;
static          bank1 unsigned char	OSCTUNE		@ 0x90;
static volatile bank1 unsigned char	LVDCON		@ 0x94;
static		bank1 unsigned char	WPUDA		@ 0x95;
static          bank1 unsigned char	IOCA		@ 0x96;
static		bank1 unsigned char	WDA		@ 0x97;
static          bank1 unsigned char	VRCON		@ 0x99;
static volatile bank1 unsigned char	EEDAT		@ 0x9A;
/* Alternate definition */
static volatile bank1 unsigned char	EEDATA		@ 0x9A;
static          bank1 unsigned char	EEADR		@ 0x9B;
/* Alternate definition */
static          bank1 unsigned char	EEADRL		@ 0x9B;
static volatile bank1 unsigned char	EECON1		@ 0x9C;
static volatile bank1 unsigned char	EECON2		@ 0x9D;
static volatile bank2 unsigned char	CRCON		@ 0x110;
static volatile bank2 unsigned char	CRDAT0		@ 0x111;
static volatile bank2 unsigned char	CRDAT1		@ 0x112;
static volatile bank2 unsigned char	CRDAT2		@ 0x113;
static volatile bank2 unsigned char	CRDAT3		@ 0x114;


/* Definitions for STATUS register */
static volatile       bit	CARRY		@ ((unsigned)&STATUS*8)+0;
static volatile       bit	DC		@ ((unsigned)&STATUS*8)+1;
static volatile       bit	ZERO		@ ((unsigned)&STATUS*8)+2;
static volatile       bit	PD		@ ((unsigned)&STATUS*8)+3;
static volatile       bit	TO		@ ((unsigned)&STATUS*8)+4;
static                bit	RP0		@ ((unsigned)&STATUS*8)+5;
static                bit	RP1		@ ((unsigned)&STATUS*8)+6;
static                bit	IRP		@ ((unsigned)&STATUS*8)+7;

#if defined(_16F636) || defined(_16F639)
/* Definitions for PORTA register */
static volatile       bit	RA0		@ ((unsigned)&PORTA*8)+0;
static volatile       bit	RA1		@ ((unsigned)&PORTA*8)+1;
static volatile       bit	RA2		@ ((unsigned)&PORTA*8)+2;
static volatile       bit	RA3		@ ((unsigned)&PORTA*8)+3;
static volatile       bit	RA4		@ ((unsigned)&PORTA*8)+4;
static volatile       bit	RA5		@ ((unsigned)&PORTA*8)+5;

/* Definitions for PORTC register */
static volatile       bit	RC0		@ ((unsigned)&PORTC*8)+0;
static volatile       bit	RC1		@ ((unsigned)&PORTC*8)+1;
static volatile       bit	RC2		@ ((unsigned)&PORTC*8)+2;
static volatile       bit	RC3		@ ((unsigned)&PORTC*8)+3;
static volatile       bit	RC4		@ ((unsigned)&PORTC*8)+4;
static volatile       bit	RC5		@ ((unsigned)&PORTC*8)+5;
#else
/* Definitions for GPIO register */
static volatile       bit	GP0		@ ((unsigned)&GPIO*8)+0;
static volatile       bit	GP1		@ ((unsigned)&GPIO*8)+1;
static volatile       bit	GP2		@ ((unsigned)&GPIO*8)+2;
static volatile       bit	GP3		@ ((unsigned)&GPIO*8)+3;
static volatile       bit	GP4		@ ((unsigned)&GPIO*8)+4;
static volatile       bit	GP5		@ ((unsigned)&GPIO*8)+5;
#endif

/* Definitions for INTCON register */
static volatile       bit	RAIF		@ ((unsigned)&INTCON*8)+0;
static volatile       bit	INTF		@ ((unsigned)&INTCON*8)+1;
static volatile       bit	T0IF		@ ((unsigned)&INTCON*8)+2;
static                bit	RAIE		@ ((unsigned)&INTCON*8)+3;
static                bit	INTE		@ ((unsigned)&INTCON*8)+4;
static                bit	T0IE		@ ((unsigned)&INTCON*8)+5;
static                bit	PEIE		@ ((unsigned)&INTCON*8)+6;
static                bit	GIE		@ ((unsigned)&INTCON*8)+7;

/* Definitions for PIR1 register */
static volatile       bit	TMR1IF		@ ((unsigned)&PIR1*8)+0;
static volatile       bit	OSFIF		@ ((unsigned)&PIR1*8)+2;
static volatile       bit	C1IF		@ ((unsigned)&PIR1*8)+3;
#if defined(_16F636) || defined(_16F639)
static volatile       bit	C2IF		@ ((unsigned)&PIR1*8)+4;
#endif
static volatile       bit	CRIF		@ ((unsigned)&PIR1*8)+5;
static volatile       bit	LVDIF		@ ((unsigned)&PIR1*8)+6;
static volatile       bit	EEIF		@ ((unsigned)&PIR1*8)+7;

/* Definitions for T1CON register */
static                bit	TMR1ON		@ ((unsigned)&T1CON*8)+0;
static                bit	TMR1CS		@ ((unsigned)&T1CON*8)+1;
static                bit	T1SYNC		@ ((unsigned)&T1CON*8)+2;
static                bit	T1OSCEN		@ ((unsigned)&T1CON*8)+3;
static                bit	T1CKPS0		@ ((unsigned)&T1CON*8)+4;
static                bit	T1CKPS1		@ ((unsigned)&T1CON*8)+5;
static                bit	TMR1GE		@ ((unsigned)&T1CON*8)+6;
static                bit	T1GINV		@ ((unsigned)&T1CON*8)+7;

/* Definitions for WDTCON register */
static                bit	SWDTEN		@ ((unsigned)&WDTCON*8)+0;
static                bit	WDTPS0		@ ((unsigned)&WDTCON*8)+1;
static                bit	WDTPS1		@ ((unsigned)&WDTCON*8)+2;
static                bit	WDTPS2		@ ((unsigned)&WDTCON*8)+3;
static                bit	WDTPS3		@ ((unsigned)&WDTCON*8)+4;

/* Definitions for CMCON0 register */
static                bit	CM0		@ ((unsigned)&CMCON0*8)+0;
static                bit	CM1		@ ((unsigned)&CMCON0*8)+1;
static                bit	CM2		@ ((unsigned)&CMCON0*8)+2;
static                bit	CIS		@ ((unsigned)&CMCON0*8)+3;
static                bit	C1INV		@ ((unsigned)&CMCON0*8)+4;
#if defined(_16F636) || defined(_16F639)
static                bit	C2INV		@ ((unsigned)&CMCON0*8)+5;
#endif
static volatile       bit	C1OUT		@ ((unsigned)&CMCON0*8)+6;
#if defined(_16F636) || defined(_16F639)
static volatile       bit	C2OUT		@ ((unsigned)&CMCON0*8)+7;
#endif

/* Definitions for CMCON1 register */
static                bit	C2SYNC		@ ((unsigned)&CMCON1*8)+0;
static                bit	T1GSS		@ ((unsigned)&CMCON1*8)+1;

/* Definitions for OPTION register */
static          bank1 bit	PS0		@ ((unsigned)&OPTION*8)+0;
static          bank1 bit	PS1		@ ((unsigned)&OPTION*8)+1;
static          bank1 bit	PS2		@ ((unsigned)&OPTION*8)+2;
static          bank1 bit	PSA		@ ((unsigned)&OPTION*8)+3;
static          bank1 bit	T0SE		@ ((unsigned)&OPTION*8)+4;
static          bank1 bit	T0CS		@ ((unsigned)&OPTION*8)+5;
static          bank1 bit	INTEDG		@ ((unsigned)&OPTION*8)+6;
static          bank1 bit	RAPU		@ ((unsigned)&OPTION*8)+7;

#if defined(_16F636) || defined(_16F639)
/* Definitions for TRISA register */
static          bank1 bit	TRISA0		@ ((unsigned)&TRISA*8)+0;
static          bank1 bit	TRISA1		@ ((unsigned)&TRISA*8)+1;
static          bank1 bit	TRISA2		@ ((unsigned)&TRISA*8)+2;
static          bank1 bit	TRISA3		@ ((unsigned)&TRISA*8)+3;
static          bank1 bit	TRISA4		@ ((unsigned)&TRISA*8)+4;
static          bank1 bit	TRISA5		@ ((unsigned)&TRISA*8)+5;

/* Definitions for TRISC register */
static volatile bank1 bit	TRISC0		@ ((unsigned)&TRISC*8)+0;
static volatile bank1 bit	TRISC1		@ ((unsigned)&TRISC*8)+1;
static volatile bank1 bit	TRISC2		@ ((unsigned)&TRISC*8)+2;
static volatile bank1 bit	TRISC3		@ ((unsigned)&TRISC*8)+3;
static volatile bank1 bit	TRISC4		@ ((unsigned)&TRISC*8)+4;
static volatile bank1 bit	TRISC5		@ ((unsigned)&TRISC*8)+5;
#else
/* Definitions for TRISIO register */
static          bank1 bit	TRISIO0		@ ((unsigned)&TRISIO*8)+0;
static          bank1 bit	TRISIO1		@ ((unsigned)&TRISIO*8)+1;
static          bank1 bit	TRISIO2		@ ((unsigned)&TRISIO*8)+2;
static          bank1 bit	TRISIO3		@ ((unsigned)&TRISIO*8)+3;
static          bank1 bit	TRISIO4		@ ((unsigned)&TRISIO*8)+4;
static          bank1 bit	TRISIO5		@ ((unsigned)&TRISIO*8)+5;
#endif

/* Definitions for PIE1 register */
static          bank1 bit	TMR1IE		@ ((unsigned)&PIE1*8)+0;
static          bank1 bit	OSFIE		@ ((unsigned)&PIE1*8)+2;
static          bank1 bit	C1IE		@ ((unsigned)&PIE1*8)+3;
#if defined(_16F636) || defined(_16F639)
static          bank1 bit	C2IE		@ ((unsigned)&PIE1*8)+4;
#endif
static		bank1 bit	CRIE		@ ((unsigned)&PIE1*8)+5;
static          bank1 bit	LVDIE		@ ((unsigned)&PIE1*8)+6;
static          bank1 bit	EEIE		@ ((unsigned)&PIE1*8)+7;

/* Definitions for PCON register */
static volatile bank1 bit	BOD		@ ((unsigned)&PCON*8)+0;
static volatile bank1 bit	POR		@ ((unsigned)&PCON*8)+1;
static volatile bank1 bit	WUR		@ ((unsigned)&PCON*8)+3;
static          bank1 bit	SBODEN		@ ((unsigned)&PCON*8)+4;
static          bank1 bit	ULPWUE		@ ((unsigned)&PCON*8)+5;

/* Definitions for OSCCON register */
static          bank1 bit	SCS		@ ((unsigned)&OSCCON*8)+0;
static volatile bank1 bit	LTS		@ ((unsigned)&OSCCON*8)+1;
static volatile bank1 bit	HTS		@ ((unsigned)&OSCCON*8)+2;
static volatile bank1 bit	OSTS		@ ((unsigned)&OSCCON*8)+3;
static          bank1 bit	IRCF0		@ ((unsigned)&OSCCON*8)+4;
static          bank1 bit	IRCF1		@ ((unsigned)&OSCCON*8)+5;
static          bank1 bit	IRCF2		@ ((unsigned)&OSCCON*8)+6;

/* Definitions for OSCTUNE register */
static          bank1 bit	TUN0		@ ((unsigned)&OSCTUNE*8)+0;
static          bank1 bit	TUN1		@ ((unsigned)&OSCTUNE*8)+1;
static          bank1 bit	TUN2		@ ((unsigned)&OSCTUNE*8)+2;
static          bank1 bit	TUN3		@ ((unsigned)&OSCTUNE*8)+3;
static          bank1 bit	TUN4		@ ((unsigned)&OSCTUNE*8)+4;

/* Definitions for LVDCON register */
static          bank1 bit	LVDL0		@ ((unsigned)&LVDCON*8)+0;
static          bank1 bit	LVDL1		@ ((unsigned)&LVDCON*8)+1;
static          bank1 bit	LVDL2		@ ((unsigned)&LVDCON*8)+2;
static          bank1 bit	LVDEN		@ ((unsigned)&LVDCON*8)+4;
static volatile bank1 bit	IRVST		@ ((unsigned)&LVDCON*8)+5;

/* Definitions for WPUDA register */
static		bank1 bit	WPUDA0		@ ((unsigned)&WPUDA*8)+0;
static		bank1 bit	WPUDA1		@ ((unsigned)&WPUDA*8)+1;
static		bank1 bit	WPUDA2		@ ((unsigned)&WPUDA*8)+2;
static		bank1 bit	WPUDA4		@ ((unsigned)&WPUDA*8)+4;
static		bank1 bit	WPUDA5		@ ((unsigned)&WPUDA*8)+5;

/* Definitions for IOCA register */
static          bank1 bit	IOCA0		@ ((unsigned)&IOCA*8)+0;
static          bank1 bit	IOCA1		@ ((unsigned)&IOCA*8)+1;
static          bank1 bit	IOCA2		@ ((unsigned)&IOCA*8)+2;
static          bank1 bit	IOCA3		@ ((unsigned)&IOCA*8)+3;
static          bank1 bit	IOCA4		@ ((unsigned)&IOCA*8)+4;
static          bank1 bit	IOCA5		@ ((unsigned)&IOCA*8)+5;

/* Definitions for WDA register */
static		bank1 bit	WDA0		@ ((unsigned)&WDA*8)+0;
static		bank1 bit	WDA1		@ ((unsigned)&WDA*8)+1;
static		bank1 bit	WDA2		@ ((unsigned)&WDA*8)+2;
static		bank1 bit	WDA4		@ ((unsigned)&WDA*8)+4;
static		bank1 bit	WDA5		@ ((unsigned)&WDA*8)+5;

/* Definitions for VRCON register */
static          bank1 bit	VR0		@ ((unsigned)&VRCON*8)+0;
static          bank1 bit	VR1		@ ((unsigned)&VRCON*8)+1;
static          bank1 bit	VR2		@ ((unsigned)&VRCON*8)+2;
static          bank1 bit	VR3		@ ((unsigned)&VRCON*8)+3;
static          bank1 bit	VRR		@ ((unsigned)&VRCON*8)+5;
static          bank1 bit	VREN		@ ((unsigned)&VRCON*8)+7;

/* Definitions for EECON1 register */
static volatile bank1 bit	RD		@ ((unsigned)&EECON1*8)+0;
static volatile bank1 bit	WR		@ ((unsigned)&EECON1*8)+1;
static          bank1 bit	WREN		@ ((unsigned)&EECON1*8)+2;
static volatile bank1 bit	WRERR		@ ((unsigned)&EECON1*8)+3;

/* Definitions for CRCON register */
static volatile bank2 bit	CRREG0		@ ((unsigned)&CRCON*8)+0;
static volatile bank2 bit	CRREG1		@ ((unsigned)&CRCON*8)+1;
static volatile bank2 bit	ENCDEC		@ ((unsigned)&CRCON*8)+6;
static volatile bank2 bit	GODONE		@ ((unsigned)&CRCON*8)+7;


// Configuration Mask Definitions
#define CONFIG_ADDR	0x2007
// Oscillator 
#define EXTCLK		0x3FFF	// External RC Clockout
#define EXTIO		0x3FFE	// External RC No Clock
#define INTCLK		0x3FFD	// Internal RC Clockout
#define INTIO		0x3FFC	// Internal RC No Clock
#define EC		0x3FFB	// EC
#define HS		0x3FFA	// HS
#define XT		0x3FF9	// XT
#define LP		0x3FF8	// LP
// Watchdog Timer 
#define WDTEN		0x3FFF	// On
#define WDTDIS		0x3FF7	// Off
// Power Up Timer 
#define PWRTDIS		0x3FFF	// Off
#define PWRTEN		0x3FEF	// On
// Master Clear Enable 
#define MCLREN		0x3FFF	// MCLR function is enabled
#define MCLRDIS		0x3FDF	// MCLR functions as IO
// Code Protect 
#define UNPROTECT	0x3FFF	// Code is not protected
#define CP		0x3FBF	// Code is protected
// Data EE Read Protect 
#define UNPROTECT	0x3FFF	// Do not read protect EEPROM data
#define CPD		0x3F7F	// Read protect EEPROM data
// Brown Out Detect 
#define BORDIS		0x3CFF	// BOD and SBOREN disabled
#define SBOREN		0x3DFF	// SBOREN controls BOR function (Software control)
#define BORXSLP		0x3EFF	// BOD enabled in run, disabled in sleep, SBOREN disabled
#define BOREN		0x3FFF	// BOD Enabled, SBOREN Disabled
// Internal External Switch Over Mode 
#define IESOEN		0x3FFF	// Enabled
#define IESODIS		0x3BFF	// Disabled
// Monitor Clock Fail-safe 
#define FCMEN		0x3FFF	// Enabled
#define FCMDIS		0x37FF	// Disabled
// Wake-Up Reset 
#define WAKECNT		0x3FFF	// Continue upon wake-up
#define WAKERST		0x2FFF	// Reset upon wake-up

#endif
