
#ifndef	_HTC_H_
#warning Header file pic12f683.h included directly. Use #include <htc.h> instead.
#endif


 /* header file for the MICROCHIP PIC microcontroller
 */

#ifndef	__PIC12F683_H
#define	__PIC12F683_H

// Special function register definitions

static volatile       unsigned char	TMR0		@ 0x01;
static volatile       unsigned char	PCL		@ 0x02;
static volatile       unsigned char	STATUS		@ 0x03;
static                unsigned char	FSR		@ 0x04;
static volatile       unsigned char	GPIO		@ 0x05;
static volatile       unsigned char	PCLATH		@ 0x0A;
static volatile       unsigned char	INTCON		@ 0x0B;
static volatile       unsigned char	PIR1		@ 0x0C;
static volatile       unsigned char	TMR1L		@ 0x0E;
static volatile       unsigned char	TMR1H		@ 0x0F;
static volatile       unsigned char	T1CON		@ 0x10;
static volatile       unsigned char	TMR2		@ 0x11;
static volatile       unsigned char	T2CON		@ 0x12;
static volatile       unsigned char	CCPR1L		@ 0x13;
static volatile       unsigned char	CCPR1H		@ 0x14;
static volatile       unsigned char	CCP1CON		@ 0x15;
static volatile       unsigned char	WDTCON		@ 0x18;
static volatile       unsigned char	CMCON0		@ 0x19;
static                unsigned char	CMCON1		@ 0x1A;
static volatile       unsigned char	ADRESH		@ 0x1E;
static volatile       unsigned char	ADCON0		@ 0x1F;
static          bank1 unsigned char	OPTION		@ 0x81;
static volatile bank1 unsigned char	TRISIO		@ 0x85;
static          bank1 unsigned char	PIE1		@ 0x8C;
static volatile bank1 unsigned char	PCON		@ 0x8E;
static volatile bank1 unsigned char	OSCCON		@ 0x8F;
static          bank1 unsigned char	OSCTUNE		@ 0x90;
static          bank1 unsigned char	PR2		@ 0x92;
static          bank1 unsigned char	WPU		@ 0x95;
static          bank1 unsigned char	IOC		@ 0x96;
static          bank1 unsigned char	VRCON		@ 0x99;
static volatile bank1 unsigned char	EEDAT		@ 0x9A;
/* Alternate definition */
static volatile bank1 unsigned char	EEDATA		@ 0x9A;
static          bank1 unsigned char	EEADR		@ 0x9B;
/* Alternate definition */
static          bank1 unsigned char	EEADRL		@ 0x9B;
static volatile bank1 unsigned char	EECON1		@ 0x9C;
static volatile bank1 unsigned char	EECON2		@ 0x9D;
static volatile bank1 unsigned char	ADRESL		@ 0x9E;
static          bank1 unsigned char	ANSEL		@ 0x9F;


/* Definitions for STATUS register */
static volatile       bit	CARRY		@ ((unsigned)&STATUS*8)+0;
static volatile       bit	DC		@ ((unsigned)&STATUS*8)+1;
static volatile       bit	ZERO		@ ((unsigned)&STATUS*8)+2;
static volatile       bit	PD		@ ((unsigned)&STATUS*8)+3;
static volatile       bit	TO		@ ((unsigned)&STATUS*8)+4;
static                bit	RP0		@ ((unsigned)&STATUS*8)+5;
static                bit	RP1		@ ((unsigned)&STATUS*8)+6;
static                bit	IRP		@ ((unsigned)&STATUS*8)+7;

/* Definitions for GPIO register */
static volatile       bit	GPIO0		@ ((unsigned)&GPIO*8)+0;
static volatile       bit	GPIO1		@ ((unsigned)&GPIO*8)+1;
static volatile       bit	GPIO2		@ ((unsigned)&GPIO*8)+2;
static volatile       bit	GPIO3		@ ((unsigned)&GPIO*8)+3;
static volatile       bit	GPIO4		@ ((unsigned)&GPIO*8)+4;
static volatile       bit	GPIO5		@ ((unsigned)&GPIO*8)+5;

/* Definitions for INTCON register */
static volatile       bit	GPIF		@ ((unsigned)&INTCON*8)+0;
static volatile       bit	INTF		@ ((unsigned)&INTCON*8)+1;
static volatile       bit	T0IF		@ ((unsigned)&INTCON*8)+2;
static                bit	GPIE		@ ((unsigned)&INTCON*8)+3;
static                bit	INTE		@ ((unsigned)&INTCON*8)+4;
static                bit	T0IE		@ ((unsigned)&INTCON*8)+5;
static                bit	PEIE		@ ((unsigned)&INTCON*8)+6;
static                bit	GIE		@ ((unsigned)&INTCON*8)+7;

/* Definitions for PIR1 register */
static volatile       bit	TMR1IF		@ ((unsigned)&PIR1*8)+0;
static volatile       bit	TMR2IF		@ ((unsigned)&PIR1*8)+1;
static volatile       bit	OSFIF		@ ((unsigned)&PIR1*8)+2;
static volatile       bit	CMIF		@ ((unsigned)&PIR1*8)+3;
static volatile       bit	CCP1IF		@ ((unsigned)&PIR1*8)+5;
static volatile       bit	ADIF		@ ((unsigned)&PIR1*8)+6;
static volatile       bit	EEIF		@ ((unsigned)&PIR1*8)+7;

/* Definitions for T1CON register */
static                bit	TMR1ON		@ ((unsigned)&T1CON*8)+0;
static                bit	TMR1CS		@ ((unsigned)&T1CON*8)+1;
static                bit	T1SYNC		@ ((unsigned)&T1CON*8)+2;
static                bit	T1OSCEN		@ ((unsigned)&T1CON*8)+3;
static                bit	T1CKPS0		@ ((unsigned)&T1CON*8)+4;
static                bit	T1CKPS1		@ ((unsigned)&T1CON*8)+5;
static                bit	T1GE		@ ((unsigned)&T1CON*8)+6;
static                bit	T1GINV		@ ((unsigned)&T1CON*8)+7;

/* Definitions for T2CON register */
static                bit	T2CKPS0		@ ((unsigned)&T2CON*8)+0;
static                bit	T2CKPS1		@ ((unsigned)&T2CON*8)+1;
static                bit	TMR2ON		@ ((unsigned)&T2CON*8)+2;
static                bit	TOUTPS0		@ ((unsigned)&T2CON*8)+3;
static                bit	TOUTPS1		@ ((unsigned)&T2CON*8)+4;
static                bit	TOUTPS2		@ ((unsigned)&T2CON*8)+5;
static                bit	TOUTPS3		@ ((unsigned)&T2CON*8)+6;

/* Definitions for CCP1CON register */
static                bit	CCP1M0		@ ((unsigned)&CCP1CON*8)+0;
static                bit	CCP1M1		@ ((unsigned)&CCP1CON*8)+1;
static                bit	CCP1M2		@ ((unsigned)&CCP1CON*8)+2;
static                bit	CCP1M3		@ ((unsigned)&CCP1CON*8)+3;
static                bit	DC1B0		@ ((unsigned)&CCP1CON*8)+4;
static                bit	DC1B1		@ ((unsigned)&CCP1CON*8)+5;

/* Definitions for WDTCON register */
static                bit	SWDTEN		@ ((unsigned)&WDTCON*8)+0;
static                bit	WDTPS0		@ ((unsigned)&WDTCON*8)+1;
static                bit	WDTPS1		@ ((unsigned)&WDTCON*8)+2;
static                bit	WDTPS2		@ ((unsigned)&WDTCON*8)+3;
static                bit	WDTPS3		@ ((unsigned)&WDTCON*8)+4;

/* Definitions for CMCON0 register */
static                bit	CM0		@ ((unsigned)&CMCON0*8)+0;
static                bit	CM1		@ ((unsigned)&CMCON0*8)+1;
static                bit	CM2		@ ((unsigned)&CMCON0*8)+2;
static                bit	CIS		@ ((unsigned)&CMCON0*8)+3;
static                bit	CINV		@ ((unsigned)&CMCON0*8)+4;
static volatile       bit	COUT		@ ((unsigned)&CMCON0*8)+6;

/* Definitions for CMCON1 register */
static                bit	CMSYNC		@ ((unsigned)&CMCON1*8)+0;
static                bit	T1GSS		@ ((unsigned)&CMCON1*8)+1;

/* Definitions for ADCON0 register */
static                bit	ADON		@ ((unsigned)&ADCON0*8)+0;
static volatile       bit	GODONE		@ ((unsigned)&ADCON0*8)+1;
static                bit	CHS0		@ ((unsigned)&ADCON0*8)+2;
static                bit	CHS1		@ ((unsigned)&ADCON0*8)+3;
static                bit	CHS2		@ ((unsigned)&ADCON0*8)+4;
static                bit	VCFG		@ ((unsigned)&ADCON0*8)+6;
static                bit	ADFM		@ ((unsigned)&ADCON0*8)+7;

/* Definitions for OPTION register */
static          bank1 bit	PS0		@ ((unsigned)&OPTION*8)+0;
static          bank1 bit	PS1		@ ((unsigned)&OPTION*8)+1;
static          bank1 bit	PS2		@ ((unsigned)&OPTION*8)+2;
static          bank1 bit	PSA		@ ((unsigned)&OPTION*8)+3;
static          bank1 bit	T0SE		@ ((unsigned)&OPTION*8)+4;
static          bank1 bit	T0CS		@ ((unsigned)&OPTION*8)+5;
static          bank1 bit	INTEDG		@ ((unsigned)&OPTION*8)+6;
static          bank1 bit	GPPU		@ ((unsigned)&OPTION*8)+7;

/* Definitions for TRISIO register */
static volatile bank1 bit	TRISIO0		@ ((unsigned)&TRISIO*8)+0;
static volatile bank1 bit	TRISIO1		@ ((unsigned)&TRISIO*8)+1;
static volatile bank1 bit	TRISIO2		@ ((unsigned)&TRISIO*8)+2;
static volatile bank1 bit	TRISIO3		@ ((unsigned)&TRISIO*8)+3;
static volatile bank1 bit	TRISIO4		@ ((unsigned)&TRISIO*8)+4;
static volatile bank1 bit	TRISIO5		@ ((unsigned)&TRISIO*8)+5;

/* Definitions for PIE1 register */
static          bank1 bit	TMR1IE		@ ((unsigned)&PIE1*8)+0;
static          bank1 bit	TMR2IE		@ ((unsigned)&PIE1*8)+1;
static          bank1 bit	OSFIE		@ ((unsigned)&PIE1*8)+2;
static          bank1 bit	CMIE		@ ((unsigned)&PIE1*8)+3;
static          bank1 bit	CCP1IE		@ ((unsigned)&PIE1*8)+5;
static          bank1 bit	ADIE		@ ((unsigned)&PIE1*8)+6;
static          bank1 bit	EEIE		@ ((unsigned)&PIE1*8)+7;

/* Definitions for PCON register */
static volatile bank1 bit	BOD		@ ((unsigned)&PCON*8)+0;
static volatile bank1 bit	POR		@ ((unsigned)&PCON*8)+1;
static          bank1 bit	SBODEN		@ ((unsigned)&PCON*8)+4;
static          bank1 bit	ULPWUE		@ ((unsigned)&PCON*8)+5;

/* Definitions for OSCCON register */
static          bank1 bit	SCS		@ ((unsigned)&OSCCON*8)+0;
static volatile bank1 bit	LTS		@ ((unsigned)&OSCCON*8)+1;
static volatile bank1 bit	HTS		@ ((unsigned)&OSCCON*8)+2;
static volatile bank1 bit	OSTS		@ ((unsigned)&OSCCON*8)+3;
static          bank1 bit	IRCF0		@ ((unsigned)&OSCCON*8)+4;
static          bank1 bit	IRCF1		@ ((unsigned)&OSCCON*8)+5;
static          bank1 bit	IRCF2		@ ((unsigned)&OSCCON*8)+6;

/* Definitions for OSCTUNE register */
static          bank1 bit	TUN0		@ ((unsigned)&OSCTUNE*8)+0;
static          bank1 bit	TUN1		@ ((unsigned)&OSCTUNE*8)+1;
static          bank1 bit	TUN2		@ ((unsigned)&OSCTUNE*8)+2;
static          bank1 bit	TUN3		@ ((unsigned)&OSCTUNE*8)+3;
static          bank1 bit	TUN4		@ ((unsigned)&OSCTUNE*8)+4;

/* Definitions for WPU register */
static          bank1 bit	WPU0		@ ((unsigned)&WPU*8)+0;
static          bank1 bit	WPU1		@ ((unsigned)&WPU*8)+1;
static          bank1 bit	WPU2		@ ((unsigned)&WPU*8)+2;
static          bank1 bit	WPU3		@ ((unsigned)&WPU*8)+3;
static          bank1 bit	WPU4		@ ((unsigned)&WPU*8)+4;
static          bank1 bit	WPU5		@ ((unsigned)&WPU*8)+5;

/* Definitions for IOC register */
static          bank1 bit	IOC0		@ ((unsigned)&IOC*8)+0;
static          bank1 bit	IOC1		@ ((unsigned)&IOC*8)+1;
static          bank1 bit	IOC2		@ ((unsigned)&IOC*8)+2;
static          bank1 bit	IOC3		@ ((unsigned)&IOC*8)+3;
static          bank1 bit	IOC4		@ ((unsigned)&IOC*8)+4;
static          bank1 bit	IOC5		@ ((unsigned)&IOC*8)+5;

/* Definitions for VRCON register */
static          bank1 bit	VR0		@ ((unsigned)&VRCON*8)+0;
static          bank1 bit	VR1		@ ((unsigned)&VRCON*8)+1;
static          bank1 bit	VR2		@ ((unsigned)&VRCON*8)+2;
static          bank1 bit	VR3		@ ((unsigned)&VRCON*8)+3;
static          bank1 bit	VRR		@ ((unsigned)&VRCON*8)+5;
static          bank1 bit	VREN		@ ((unsigned)&VRCON*8)+7;

/* Definitions for EECON1 register */
static volatile bank1 bit	RD		@ ((unsigned)&EECON1*8)+0;
static volatile bank1 bit	WR		@ ((unsigned)&EECON1*8)+1;
static          bank1 bit	WREN		@ ((unsigned)&EECON1*8)+2;
static volatile bank1 bit	WRERR		@ ((unsigned)&EECON1*8)+3;

/* Definitions for ANSEL register */
static          bank1 bit	ANS0		@ ((unsigned)&ANSEL*8)+0;
static          bank1 bit	ANS1		@ ((unsigned)&ANSEL*8)+1;
static          bank1 bit	ANS2		@ ((unsigned)&ANSEL*8)+2;
static          bank1 bit	ANS3		@ ((unsigned)&ANSEL*8)+3;
static          bank1 bit	ADCS0		@ ((unsigned)&ANSEL*8)+4;
static          bank1 bit	ADCS1		@ ((unsigned)&ANSEL*8)+5;
static          bank1 bit	ADCS2		@ ((unsigned)&ANSEL*8)+6;


// Configuration Mask Definitions
#define CONFIG_ADDR	0x2007
// Fail Clock Monitor Enable 
#define FCMEN		0x3FFF
#define FCMDIS		0x37FF
// Internal External Switch Over 
#define IESOEN		0x3FFF
#define IESODIS		0x3BFF
// Brown-out detect modes 
#define BOREN		0x3FFF
#define BOREN_XSLP	0x3EFF
#define SBOREN		0x3DFF
#define BORDIS		0x3CFF
// Protection of data block 
#define UNPROTECT	0x3FFF
#define CPD		0x3F7F
// Protection of program code 
#define UNPROTECT	0x3FFF
#define PROTECT		0x3FBF
// Master clear reset
#define MCLREN		0x3FFF
#define MCLRDIS		0x3FDF
// Power up timer enable 
#define PWRTDIS		0x3FFF
#define PWRTEN		0x3FEF
// Watchdog timer enable 
#define WDTEN		0x3FFF
#define WDTDIS		0x3FF7
// Oscillator configurations 
#define RCCLK		0x3FFF
#define RCIO		0x3FFE
#define INTCLK		0x3FFD
#define INTIO		0x3FFC
#define EC		0x3FFB
#define HS		0x3FFA
#define XT		0x3FF9
#define LP		0x3FF8

#endif
