
#ifndef	_HTC_H_
#warning Header file pic16f87.h included directly. Use #include <htc.h> instead.
#endif

 /* header file for the MICROCHIP PIC microcontrollers
	PIC16F87
	PIC16F88
 */

#ifndef	__PIC16F87_H
#define	__PIC16F87_H

// Special function register definitions

static volatile       unsigned char	TMR0		@ 0x01;
static volatile       unsigned char	PCL		@ 0x02;
static volatile       unsigned char	STATUS		@ 0x03;
static                unsigned char	FSR		@ 0x04;
static volatile       unsigned char	PORTA		@ 0x05;
static volatile       unsigned char	PORTB		@ 0x06;
static volatile       unsigned char	PCLATH		@ 0x0A;
static volatile       unsigned char	INTCON		@ 0x0B;
static volatile       unsigned char	PIR1		@ 0x0C;
static volatile       unsigned char	PIR2		@ 0x0D;
static volatile       unsigned char	TMR1L		@ 0x0E;
static volatile       unsigned char	TMR1H		@ 0x0F;
static volatile       unsigned char	T1CON		@ 0x10;
static volatile       unsigned char	TMR2		@ 0x11;
static volatile       unsigned char	T2CON		@ 0x12;
static volatile       unsigned char	SSPBUF		@ 0x13;
static volatile       unsigned char	SSPCON		@ 0x14;
static volatile       unsigned char	CCPR1L		@ 0x15;
static volatile       unsigned char	CCPR1H		@ 0x16;
static volatile       unsigned char	CCP1CON		@ 0x17;
static volatile       unsigned char	RCSTA		@ 0x18;
static volatile       unsigned char	TXREG		@ 0x19;
static volatile       unsigned char	RCREG		@ 0x1A;
#if defined(_16F88)
static volatile       unsigned char	ADRESH		@ 0x1E;
static volatile       unsigned char	ADCON0		@ 0x1F;
#endif
static          bank1 unsigned char	OPTION		@ 0x81;
static volatile bank1 unsigned char	TRISA		@ 0x85;
static volatile bank1 unsigned char	TRISB		@ 0x86;
static          bank1 unsigned char	PIE1		@ 0x8C;
static          bank1 unsigned char	PIE2		@ 0x8D;
static volatile bank1 unsigned char	PCON		@ 0x8E;
static volatile bank1 unsigned char	OSCCON		@ 0x8F;
static          bank1 unsigned char	OSCTUNE		@ 0x90;
static          bank1 unsigned char	PR2		@ 0x92;
static          bank1 unsigned char	SSPADD		@ 0x93;
static volatile bank1 unsigned char	SSPSTAT		@ 0x94;
static volatile bank1 unsigned char	TXSTA		@ 0x98;
static          bank1 unsigned char	SPBRG		@ 0x99;
#if defined(_16F88)
static          bank1 unsigned char	ANSEL		@ 0x9B;
#endif
static volatile bank1 unsigned char	CMCON		@ 0x9C;
static volatile bank1 unsigned char	CVRCON		@ 0x9D;
#if defined(_16F88)
static volatile bank1 unsigned char	ADRESL		@ 0x9E;
static          bank1 unsigned char	ADCON1		@ 0x9F;
#endif
static volatile bank2 unsigned char	WDTCON		@ 0x105;
static volatile bank2 unsigned char	EEDATA		@ 0x10C;
static          bank2 unsigned char	EEADR		@ 0x10D;
static volatile bank2 unsigned char	EEDATH		@ 0x10E;
static          bank2 unsigned char	EEADRH		@ 0x10F;
static volatile bank3 unsigned char	EECON1		@ 0x18C;
static volatile bank3 unsigned char	EECON2		@ 0x18D;


/* Definitions for STATUS register */
static volatile       bit	CARRY		@ ((unsigned)&STATUS*8)+0;
static volatile       bit	DC		@ ((unsigned)&STATUS*8)+1;
static volatile       bit	ZERO		@ ((unsigned)&STATUS*8)+2;
static volatile       bit	PD		@ ((unsigned)&STATUS*8)+3;
static volatile       bit	TO		@ ((unsigned)&STATUS*8)+4;
static                bit	RP0		@ ((unsigned)&STATUS*8)+5;
static                bit	RP1		@ ((unsigned)&STATUS*8)+6;
static                bit	IRP		@ ((unsigned)&STATUS*8)+7;

/* Definitions for PORTA register */
static volatile       bit	RA0		@ ((unsigned)&PORTA*8)+0;
static volatile       bit	RA1		@ ((unsigned)&PORTA*8)+1;
static volatile       bit	RA2		@ ((unsigned)&PORTA*8)+2;
static volatile       bit	RA3		@ ((unsigned)&PORTA*8)+3;
static volatile       bit	RA4		@ ((unsigned)&PORTA*8)+4;
static volatile       bit	RA5		@ ((unsigned)&PORTA*8)+5;
static volatile       bit	RA6		@ ((unsigned)&PORTA*8)+6;
static volatile       bit	RA7		@ ((unsigned)&PORTA*8)+7;

/* Definitions for PORTB register */
static volatile       bit	RB0		@ ((unsigned)&PORTB*8)+0;
static volatile       bit	RB1		@ ((unsigned)&PORTB*8)+1;
static volatile       bit	RB2		@ ((unsigned)&PORTB*8)+2;
static volatile       bit	RB3		@ ((unsigned)&PORTB*8)+3;
static volatile       bit	RB4		@ ((unsigned)&PORTB*8)+4;
static volatile       bit	RB5		@ ((unsigned)&PORTB*8)+5;
static volatile       bit	RB6		@ ((unsigned)&PORTB*8)+6;
static volatile       bit	RB7		@ ((unsigned)&PORTB*8)+7;

/* Definitions for INTCON register */
static volatile       bit	RBIF		@ ((unsigned)&INTCON*8)+0;
static volatile       bit	INT0IF		@ ((unsigned)&INTCON*8)+1;
static volatile       bit	TMR0IF		@ ((unsigned)&INTCON*8)+2;
static                bit	RBIE		@ ((unsigned)&INTCON*8)+3;
static                bit	INT0IE		@ ((unsigned)&INTCON*8)+4;
static                bit	TMR0IE		@ ((unsigned)&INTCON*8)+5;
static                bit	PEIE		@ ((unsigned)&INTCON*8)+6;
static                bit	GIE		@ ((unsigned)&INTCON*8)+7;

/* Definitions for PIR1 register */
static volatile       bit	TMR1IF		@ ((unsigned)&PIR1*8)+0;
static volatile       bit	TMR2IF		@ ((unsigned)&PIR1*8)+1;
static volatile       bit	CCP1IF		@ ((unsigned)&PIR1*8)+2;
static volatile       bit	SSPIF		@ ((unsigned)&PIR1*8)+3;
static volatile       bit	TXIF		@ ((unsigned)&PIR1*8)+4;
static volatile       bit	RCIF		@ ((unsigned)&PIR1*8)+5;
static volatile       bit	ADIF		@ ((unsigned)&PIR1*8)+6;

/* Definitions for PIR2 register */
static volatile       bit	EEIF		@ ((unsigned)&PIR2*8)+4;
static volatile       bit	CMIF		@ ((unsigned)&PIR2*8)+6;
static volatile       bit	OSFIF		@ ((unsigned)&PIR2*8)+7;

/* Definitions for T1CON register */
static                bit	TMR1ON		@ ((unsigned)&T1CON*8)+0;
static                bit	TMR1CS		@ ((unsigned)&T1CON*8)+1;
static                bit	T1SYNC		@ ((unsigned)&T1CON*8)+2;
static                bit	T1OSCEN		@ ((unsigned)&T1CON*8)+3;
static                bit	T1CKPS0		@ ((unsigned)&T1CON*8)+4;
static                bit	T1CKPS1		@ ((unsigned)&T1CON*8)+5;
static                bit	T1RUN		@ ((unsigned)&T1CON*8)+6;

/* Definitions for T2CON register */
static                bit	T2CKPS0		@ ((unsigned)&T2CON*8)+0;
static                bit	T2CKPS1		@ ((unsigned)&T2CON*8)+1;
static                bit	TMR2ON		@ ((unsigned)&T2CON*8)+2;
static                bit	TOUTPS0		@ ((unsigned)&T2CON*8)+3;
static                bit	TOUTPS1		@ ((unsigned)&T2CON*8)+4;
static                bit	TOUTPS2		@ ((unsigned)&T2CON*8)+5;
static                bit	TOUTPS3		@ ((unsigned)&T2CON*8)+6;

/* Definitions for SSPCON register */
static                bit	SSPM0		@ ((unsigned)&SSPCON*8)+0;
static                bit	SSPM1		@ ((unsigned)&SSPCON*8)+1;
static                bit	SSPM2		@ ((unsigned)&SSPCON*8)+2;
static                bit	SSPM3		@ ((unsigned)&SSPCON*8)+3;
static                bit	CKP		@ ((unsigned)&SSPCON*8)+4;
static                bit	SSPEN		@ ((unsigned)&SSPCON*8)+5;
static volatile       bit	SSPOV		@ ((unsigned)&SSPCON*8)+6;
static volatile       bit	WCOL		@ ((unsigned)&SSPCON*8)+7;

/* Definitions for CCP1CON register */
static                bit	CCP1M0		@ ((unsigned)&CCP1CON*8)+0;
static                bit	CCP1M1		@ ((unsigned)&CCP1CON*8)+1;
static                bit	CCP1M2		@ ((unsigned)&CCP1CON*8)+2;
static                bit	CCP1M3		@ ((unsigned)&CCP1CON*8)+3;
static volatile       bit	CCP1Y		@ ((unsigned)&CCP1CON*8)+4;
static volatile       bit	CCP1X		@ ((unsigned)&CCP1CON*8)+5;

/* Definitions for RCSTA register */
static volatile       bit	RX9D		@ ((unsigned)&RCSTA*8)+0;
static volatile       bit	OERR		@ ((unsigned)&RCSTA*8)+1;
static volatile       bit	FERR		@ ((unsigned)&RCSTA*8)+2;
static                bit	ADDEN		@ ((unsigned)&RCSTA*8)+3;
static                bit	CREN		@ ((unsigned)&RCSTA*8)+4;
static                bit	SREN		@ ((unsigned)&RCSTA*8)+5;
static                bit	RX9		@ ((unsigned)&RCSTA*8)+6;
static                bit	SPEN		@ ((unsigned)&RCSTA*8)+7;

#if defined(_16F88)
/* Definitions for ADCON0 register */
static                bit	ADON		@ ((unsigned)&ADCON0*8)+0;
static volatile       bit	GODONE		@ ((unsigned)&ADCON0*8)+2;
static                bit	CHS0		@ ((unsigned)&ADCON0*8)+3;
static                bit	CHS1		@ ((unsigned)&ADCON0*8)+4;
static                bit	CHS2		@ ((unsigned)&ADCON0*8)+5;
static                bit	ADCS0		@ ((unsigned)&ADCON0*8)+6;
static                bit	ADCS1		@ ((unsigned)&ADCON0*8)+7;
/* Alternate definitions for ADCON0 register */
static volatile       bit	ADGO		@ ((unsigned)&ADCON0*8)+2;
#endif

/* Definitions for OPTION register */
static          bank1 bit	PS0		@ ((unsigned)&OPTION*8)+0;
static          bank1 bit	PS1		@ ((unsigned)&OPTION*8)+1;
static          bank1 bit	PS2		@ ((unsigned)&OPTION*8)+2;
static          bank1 bit	PSA		@ ((unsigned)&OPTION*8)+3;
static          bank1 bit	T0SE		@ ((unsigned)&OPTION*8)+4;
static          bank1 bit	T0CS		@ ((unsigned)&OPTION*8)+5;
static          bank1 bit	INTEDG		@ ((unsigned)&OPTION*8)+6;
static          bank1 bit	RBPU		@ ((unsigned)&OPTION*8)+7;

/* Definitions for TRISA register */
static volatile bank1 bit	TRISA0		@ ((unsigned)&TRISA*8)+0;
static volatile bank1 bit	TRISA1		@ ((unsigned)&TRISA*8)+1;
static volatile bank1 bit	TRISA2		@ ((unsigned)&TRISA*8)+2;
static volatile bank1 bit	TRISA3		@ ((unsigned)&TRISA*8)+3;
static volatile bank1 bit	TRISA4		@ ((unsigned)&TRISA*8)+4;
static volatile bank1 bit	TRISA5		@ ((unsigned)&TRISA*8)+5;
static volatile bank1 bit	TRISA6		@ ((unsigned)&TRISA*8)+6;
static volatile bank1 bit	TRISA7		@ ((unsigned)&TRISA*8)+7;

/* Definitions for TRISB register */
static volatile bank1 bit	TRISB0		@ ((unsigned)&TRISB*8)+0;
static volatile bank1 bit	TRISB1		@ ((unsigned)&TRISB*8)+1;
static volatile bank1 bit	TRISB2		@ ((unsigned)&TRISB*8)+2;
static volatile bank1 bit	TRISB3		@ ((unsigned)&TRISB*8)+3;
static volatile bank1 bit	TRISB4		@ ((unsigned)&TRISB*8)+4;
static volatile bank1 bit	TRISB5		@ ((unsigned)&TRISB*8)+5;
static volatile bank1 bit	TRISB6		@ ((unsigned)&TRISB*8)+6;
static volatile bank1 bit	TRISB7		@ ((unsigned)&TRISB*8)+7;

/* Definitions for PIE1 register */
static          bank1 bit	TMR1IE		@ ((unsigned)&PIE1*8)+0;
static          bank1 bit	TMR2IE		@ ((unsigned)&PIE1*8)+1;
static          bank1 bit	CCP1IE		@ ((unsigned)&PIE1*8)+2;
static          bank1 bit	SSPIE		@ ((unsigned)&PIE1*8)+3;
static          bank1 bit	TXIE		@ ((unsigned)&PIE1*8)+4;
static          bank1 bit	RCIE		@ ((unsigned)&PIE1*8)+5;
static          bank1 bit	ADIE		@ ((unsigned)&PIE1*8)+6;

/* Definitions for PIE2 register */
static          bank1 bit	EEIE		@ ((unsigned)&PIE2*8)+4;
static          bank1 bit	CMIE		@ ((unsigned)&PIE2*8)+6;
static          bank1 bit	OSFIE		@ ((unsigned)&PIE2*8)+7;

/* Definitions for PCON register */
static volatile bank1 bit	BOR		@ ((unsigned)&PCON*8)+0;
static volatile bank1 bit	POR		@ ((unsigned)&PCON*8)+1;

/* Definitions for OSCCON register */
static          bank1 bit	SCS0		@ ((unsigned)&OSCCON*8)+0;
static          bank1 bit	SCS1		@ ((unsigned)&OSCCON*8)+1;
static volatile bank1 bit	IOFS		@ ((unsigned)&OSCCON*8)+2;
static volatile bank1 bit	OSTS		@ ((unsigned)&OSCCON*8)+3;
static          bank1 bit	IRCF0		@ ((unsigned)&OSCCON*8)+4;
static          bank1 bit	IRCF1		@ ((unsigned)&OSCCON*8)+5;
static          bank1 bit	IRCF2		@ ((unsigned)&OSCCON*8)+6;

/* Definitions for OSCTUNE register */
static          bank1 bit	TUN0		@ ((unsigned)&OSCTUNE*8)+0;
static          bank1 bit	TUN1		@ ((unsigned)&OSCTUNE*8)+1;
static          bank1 bit	TUN2		@ ((unsigned)&OSCTUNE*8)+2;
static          bank1 bit	TUN3		@ ((unsigned)&OSCTUNE*8)+3;
static          bank1 bit	TUN4		@ ((unsigned)&OSCTUNE*8)+4;
static          bank1 bit	TUN5		@ ((unsigned)&OSCTUNE*8)+5;

/* Definitions for SSPSTAT register */
static volatile bank1 bit	BF		@ ((unsigned)&SSPSTAT*8)+0;
static volatile bank1 bit	UA		@ ((unsigned)&SSPSTAT*8)+1;
static volatile bank1 bit	RW		@ ((unsigned)&SSPSTAT*8)+2;
static volatile bank1 bit	START		@ ((unsigned)&SSPSTAT*8)+3;
static volatile bank1 bit	STOP		@ ((unsigned)&SSPSTAT*8)+4;
static volatile bank1 bit	DA		@ ((unsigned)&SSPSTAT*8)+5;
static          bank1 bit	CKE		@ ((unsigned)&SSPSTAT*8)+6;
static          bank1 bit	SMP		@ ((unsigned)&SSPSTAT*8)+7;

/* Definitions for TXSTA register */
static volatile bank1 bit	TX9D		@ ((unsigned)&TXSTA*8)+0;
static volatile bank1 bit	TRMT		@ ((unsigned)&TXSTA*8)+1;
static          bank1 bit	BRGH		@ ((unsigned)&TXSTA*8)+2;
static          bank1 bit	SYNC		@ ((unsigned)&TXSTA*8)+4;
static          bank1 bit	TXEN		@ ((unsigned)&TXSTA*8)+5;
static          bank1 bit	TX9		@ ((unsigned)&TXSTA*8)+6;
static          bank1 bit	CSRC		@ ((unsigned)&TXSTA*8)+7;

#if defined(_16F88)
/* Definitions for ANSEL register */
static          bank1 bit	ANS0		@ ((unsigned)&ANSEL*8)+0;
static          bank1 bit	ANS1		@ ((unsigned)&ANSEL*8)+1;
static          bank1 bit	ANS2		@ ((unsigned)&ANSEL*8)+2;
static          bank1 bit	ANS3		@ ((unsigned)&ANSEL*8)+3;
static          bank1 bit	ANS4		@ ((unsigned)&ANSEL*8)+4;
static          bank1 bit	ANS5		@ ((unsigned)&ANSEL*8)+5;
static          bank1 bit	ANS6		@ ((unsigned)&ANSEL*8)+6;
#endif

/* Definitions for CMCON register */
static          bank1 bit	CM0		@ ((unsigned)&CMCON*8)+0;
static          bank1 bit	CM1		@ ((unsigned)&CMCON*8)+1;
static          bank1 bit	CM2		@ ((unsigned)&CMCON*8)+2;
static          bank1 bit	CIS		@ ((unsigned)&CMCON*8)+3;
static          bank1 bit	C1INV		@ ((unsigned)&CMCON*8)+4;
static          bank1 bit	C2INV		@ ((unsigned)&CMCON*8)+5;
static volatile bank1 bit	C1OUT		@ ((unsigned)&CMCON*8)+6;
static volatile bank1 bit	C2OUT		@ ((unsigned)&CMCON*8)+7;

/* Definitions for CVRCON register */
static          bank1 bit	CVR0		@ ((unsigned)&CVRCON*8)+0;
static          bank1 bit	CVR1		@ ((unsigned)&CVRCON*8)+1;
static          bank1 bit	CVR2		@ ((unsigned)&CVRCON*8)+2;
static          bank1 bit	CVR3		@ ((unsigned)&CVRCON*8)+3;
static          bank1 bit	CVRR		@ ((unsigned)&CVRCON*8)+5;
static          bank1 bit	CVROE		@ ((unsigned)&CVRCON*8)+6;
static          bank1 bit	CVREN		@ ((unsigned)&CVRCON*8)+7;

#if defined(_16F88)
/* Definitions for ADCON1 register */
static          bank1 bit	VCFG0		@ ((unsigned)&ADCON1*8)+4;
static          bank1 bit	VCFG1		@ ((unsigned)&ADCON1*8)+5;
static          bank1 bit	ADCS2		@ ((unsigned)&ADCON1*8)+6;
static          bank1 bit	ADFM		@ ((unsigned)&ADCON1*8)+7;
#endif

/* Definitions for WDTCON register */
static          bank2 bit	SWDTEN		@ ((unsigned)&WDTCON*8)+0;
static          bank2 bit	WDTPS0		@ ((unsigned)&WDTCON*8)+1;
static          bank2 bit	WDTPS1		@ ((unsigned)&WDTCON*8)+2;
static          bank2 bit	WDTPS2		@ ((unsigned)&WDTCON*8)+3;
static          bank2 bit	WDTPS3		@ ((unsigned)&WDTCON*8)+4;

/* Definitions for EECON1 register */
static volatile bank3 bit	RD		@ ((unsigned)&EECON1*8)+0;
static volatile bank3 bit	WR		@ ((unsigned)&EECON1*8)+1;
static          bank3 bit	WREN		@ ((unsigned)&EECON1*8)+2;
static volatile bank3 bit	WRERR		@ ((unsigned)&EECON1*8)+3;
static volatile bank3 bit	FREE		@ ((unsigned)&EECON1*8)+4;
static          bank3 bit	EEPGD		@ ((unsigned)&EECON1*8)+7;

					
// Configuration Mask Definitions
#define CONFIG_ADDR	0x2007
// Protection of program code 
#define PROTECT		0x1FFF
#define UNPROTECT	0x3FFF
// CCP1 Pin selection 
#define CCPRB0		0x3FFF
#define CCPRB3		0x2FFF
// In-Circuit Debugger Mode 
#define DEBUGEN		0x37FF
#define DEBUGDIS	0x3FFF
// Flash Program Memory Write Enable 
#define UNPROTECT	0x3FFF
#define WP0		0x3DFF
#define WP1		0x3BFF
#define WPA		0x39FF
// Data EE Memory Code Protection 
#define UNPROTECT	0x3FFF
#define CPD		0x3EFF
// Low Voltage Programming Enable 
#define LVPEN		0x3FFF
#define LVPDIS		0x3F7F
// Brown out detection enable 
#define BOREN		0x3FFF
#define BORDIS		0x3FBF
// Master clear reset pin function
#define MCLREN		0x3FFF
#define MCLRDIS		0x3FDF
// Power up timer enable 
#define PWRTDIS		0x3FFF
#define PWRTEN		0x3FF7
// Watchdog timer enable 
#define WDTEN		0x3FFF
#define WDTDIS		0x3FFB
// Oscillator configurations 
#define RCCLK		0x3FFF
#define RCIO		0x3FFE
#define INTCLK		0x3FFD
#define INTIO		0x3FFC
#define EC		0x3FEF
#define HS		0x3FEE
#define XT		0x3FED
#define LP		0x3FEC

#define CONFIG_ADDR2	0x2008
// Fail Clock Monitor Enable 
#define FCMEN		0x3FFF
#define FCMDIS		0x3FFE
// Internal External Switch Over 
#define IESOEN		0x3FFF
#define IESODIS		0x3FFD



#endif
