
#ifndef	_HTC_H_
#warning Header file pic16f946.h included directly. Use #include <htc.h> instead.
#endif

 /* header file for the MICROCHIP PIC microcontroller
 */

#ifndef	__PIC16F946_H
#define	__PIC16F946_H

// Special function register definitions

static volatile       unsigned char	TMR0		@ 0x001;
static volatile       unsigned char	PCL		@ 0x002;
static volatile       unsigned char	STATUS		@ 0x003;
static                unsigned char	FSR		@ 0x004;
static volatile       unsigned char	PORTA		@ 0x005;
static volatile       unsigned char	PORTB		@ 0x006;
static volatile       unsigned char	PORTC		@ 0x007;
static volatile       unsigned char	PORTD		@ 0x008;
static volatile       unsigned char	PORTE		@ 0x009;
static volatile       unsigned char	PCLATH		@ 0x00A;
static volatile       unsigned char	INTCON		@ 0x00B;
static volatile       unsigned char	PIR1		@ 0x00C;
static volatile       unsigned char	PIR2		@ 0x00D;
static volatile       unsigned char	TMR1L		@ 0x00E;
static volatile       unsigned char	TMR1H		@ 0x00F;
static                unsigned char	T1CON		@ 0x010;
static volatile       unsigned char	TMR2		@ 0x011;
static                unsigned char	T2CON		@ 0x012;
static volatile       unsigned char	SSPBUF		@ 0x013;
static volatile       unsigned char	SSPCON		@ 0x014;
static volatile       unsigned char	CCPR1L		@ 0x015;
static volatile       unsigned char	CCPR1H		@ 0x016;
static volatile       unsigned char	CCP1CON		@ 0x017;
static volatile       unsigned char	RCSTA		@ 0x018;
static volatile       unsigned char	TXREG		@ 0x019;
static volatile       unsigned char	RCREG		@ 0x01A;
static volatile       unsigned char	CCPR2L		@ 0x01B;
static volatile       unsigned char	CCPR2H		@ 0x01C;
static volatile       unsigned char	CCP2CON		@ 0x01D;
static volatile       unsigned char	ADRESH		@ 0x01E;
static volatile       unsigned char	ADCON0		@ 0x01F;
static          bank1 unsigned char	OPTION		@ 0x081;
static volatile bank1 unsigned char	TRISA		@ 0x085;
static volatile bank1 unsigned char	TRISB		@ 0x086;
static volatile bank1 unsigned char	TRISC		@ 0x087;
static volatile bank1 unsigned char	TRISD		@ 0x088;
static volatile bank1 unsigned char	TRISE		@ 0x089;
static          bank1 unsigned char	PIE1		@ 0x08C;
static          bank1 unsigned char	PIE2		@ 0x08D;
static volatile bank1 unsigned char	PCON		@ 0x08E;
static volatile bank1 unsigned char	OSCCON		@ 0x08F;
static          bank1 unsigned char	OSCTUNE		@ 0x090;
static          bank1 unsigned char	ANSEL		@ 0x091;
static          bank1 unsigned char	PR2		@ 0x092;
static          bank1 unsigned char	SSPADD		@ 0x093;
static volatile bank1 unsigned char	SSPSTAT		@ 0x094;
static          bank1 unsigned char	WPUB		@ 0x095;
static          bank1 unsigned char	IOCB		@ 0x096;
static          bank1 unsigned char	CMCON1		@ 0x097;
static volatile bank1 unsigned char	TXSTA		@ 0x098;
static          bank1 unsigned char	SPBRG		@ 0x099;
static volatile bank1 unsigned char	CMCON0		@ 0x09C;
static          bank1 unsigned char	VRCON		@ 0x09D;
static volatile bank1 unsigned char	ADRESL		@ 0x09E;
static          bank1 unsigned char	ADCON1		@ 0x09F;
static volatile bank2 unsigned char	WDTCON		@ 0x105;
static volatile bank2 unsigned char	LCDCON		@ 0x107;
static volatile bank2 unsigned char	LCDPS		@ 0x108;
static volatile bank2 unsigned char	LVDCON		@ 0x109;
static volatile bank2 unsigned char	EEDATL		@ 0x10C;
/* Alternate definition */
static volatile bank2 unsigned char	EEDATA		@ 0x10C;
static          bank2 unsigned char	EEADRL		@ 0x10D;
/* Alternate definition */
static          bank2 unsigned char	EEADR		@ 0x10D;
static volatile bank2 unsigned char	EEDATH		@ 0x10E;
static          bank2 unsigned char	EEADRH		@ 0x10F;
static          bank2 unsigned char	LCDDATA0	@ 0x110;
static          bank2 unsigned char	LCDDATA1	@ 0x111;
static          bank2 unsigned char	LCDDATA2	@ 0x112;
static          bank2 unsigned char	LCDDATA3	@ 0x113;
static          bank2 unsigned char	LCDDATA4	@ 0x114;
static          bank2 unsigned char	LCDDATA5	@ 0x115;
static          bank2 unsigned char	LCDDATA6	@ 0x116;
static          bank2 unsigned char	LCDDATA7	@ 0x117;
static          bank2 unsigned char	LCDDATA8	@ 0x118;
static          bank2 unsigned char	LCDDATA9	@ 0x119;
static          bank2 unsigned char	LCDDATA10	@ 0x11A;
static          bank2 unsigned char	LCDDATA11	@ 0x11B;
static          bank2 unsigned char	LCDSE0		@ 0x11C;
static          bank2 unsigned char	LCDSE1		@ 0x11D;
static          bank2 unsigned char	LCDSE2		@ 0x11E;
static volatile bank3 unsigned char	TRISF		@ 0x185;
static volatile bank3 unsigned char	TRISG		@ 0x187;
static volatile bank3 unsigned char	PORTF		@ 0x188;
static volatile bank3 unsigned char	PORTG		@ 0x189;
static volatile bank3 unsigned char	EECON1		@ 0x18C;
static volatile bank3 unsigned char	EECON2		@ 0x18D;
static          bank3 unsigned char	LCDDATA12	@ 0x190;
static          bank3 unsigned char	LCDDATA13	@ 0x191;
static          bank3 unsigned char	LCDDATA14	@ 0x192;
static          bank3 unsigned char	LCDDATA15	@ 0x193;
static          bank3 unsigned char	LCDDATA16	@ 0x194;
static          bank3 unsigned char	LCDDATA17	@ 0x195;
static          bank3 unsigned char	LCDDATA18	@ 0x196;
static          bank3 unsigned char	LCDDATA19	@ 0x197;
static          bank3 unsigned char	LCDDATA20	@ 0x198;
static          bank3 unsigned char	LCDDATA21	@ 0x199;
static          bank3 unsigned char	LCDDATA22	@ 0x19A;
static          bank3 unsigned char	LCDDATA23	@ 0x19B;
static          bank3 unsigned char	LCDSE3		@ 0x19C;
static          bank3 unsigned char	LCDSE4		@ 0x19D;
static          bank3 unsigned char	LCDSE5		@ 0x19E;


/* Definitions for STATUS register */
static volatile       bit	CARRY		@ ((unsigned)&STATUS*8)+0;
static volatile       bit	DC		@ ((unsigned)&STATUS*8)+1;
static volatile       bit	ZERO		@ ((unsigned)&STATUS*8)+2;
static volatile       bit	PD		@ ((unsigned)&STATUS*8)+3;
static volatile       bit	TO		@ ((unsigned)&STATUS*8)+4;
static                bit	RP0		@ ((unsigned)&STATUS*8)+5;
static                bit	RP1		@ ((unsigned)&STATUS*8)+6;
static                bit	IRP		@ ((unsigned)&STATUS*8)+7;

/* Definitions for PORTA register */
static volatile       bit	RA0		@ ((unsigned)&PORTA*8)+0;
static volatile       bit	RA1		@ ((unsigned)&PORTA*8)+1;
static volatile       bit	RA2		@ ((unsigned)&PORTA*8)+2;
static volatile       bit	RA3		@ ((unsigned)&PORTA*8)+3;
static volatile       bit	RA4		@ ((unsigned)&PORTA*8)+4;
static volatile       bit	RA5		@ ((unsigned)&PORTA*8)+5;
static volatile       bit	RA6		@ ((unsigned)&PORTA*8)+6;
static volatile       bit	RA7		@ ((unsigned)&PORTA*8)+7;

/* Definitions for PORTB register */
static volatile       bit	RB0		@ ((unsigned)&PORTB*8)+0;
static volatile       bit	RB1		@ ((unsigned)&PORTB*8)+1;
static volatile       bit	RB2		@ ((unsigned)&PORTB*8)+2;
static volatile       bit	RB3		@ ((unsigned)&PORTB*8)+3;
static volatile       bit	RB4		@ ((unsigned)&PORTB*8)+4;
static volatile       bit	RB5		@ ((unsigned)&PORTB*8)+5;
static volatile       bit	RB6		@ ((unsigned)&PORTB*8)+6;
static volatile       bit	RB7		@ ((unsigned)&PORTB*8)+7;

/* Definitions for PORTC register */
static volatile       bit	RC0		@ ((unsigned)&PORTC*8)+0;
static volatile       bit	RC1		@ ((unsigned)&PORTC*8)+1;
static volatile       bit	RC2		@ ((unsigned)&PORTC*8)+2;
static volatile       bit	RC3		@ ((unsigned)&PORTC*8)+3;
static volatile       bit	RC4		@ ((unsigned)&PORTC*8)+4;
static volatile       bit	RC5		@ ((unsigned)&PORTC*8)+5;
static volatile       bit	RC6		@ ((unsigned)&PORTC*8)+6;
static volatile       bit	RC7		@ ((unsigned)&PORTC*8)+7;

/* Definitions for PORTD register */
static volatile       bit	RD0		@ ((unsigned)&PORTD*8)+0;
static volatile       bit	RD1		@ ((unsigned)&PORTD*8)+1;
static volatile       bit	RD2		@ ((unsigned)&PORTD*8)+2;
static volatile       bit	RD3		@ ((unsigned)&PORTD*8)+3;
static volatile       bit	RD4		@ ((unsigned)&PORTD*8)+4;
static volatile       bit	RD5		@ ((unsigned)&PORTD*8)+5;
static volatile       bit	RD6		@ ((unsigned)&PORTD*8)+6;
static volatile       bit	RD7		@ ((unsigned)&PORTD*8)+7;

/* Definitions for PORTE register */
static volatile       bit	RE0		@ ((unsigned)&PORTE*8)+0;
static volatile       bit	RE1		@ ((unsigned)&PORTE*8)+1;
static volatile       bit	RE2		@ ((unsigned)&PORTE*8)+2;
static volatile       bit	RE3		@ ((unsigned)&PORTE*8)+3;
static volatile       bit	RE4		@ ((unsigned)&PORTE*8)+4;
static volatile       bit	RE5		@ ((unsigned)&PORTE*8)+5;
static volatile       bit	RE6		@ ((unsigned)&PORTE*8)+6;
static volatile       bit	RE7		@ ((unsigned)&PORTE*8)+7;

/* Definitions for INTCON register */
static volatile       bit	RBIF		@ ((unsigned)&INTCON*8)+0;
// Alternate definition for backward compatibility
static volatile       bit	RABIF		@ ((unsigned)&INTCON*8)+0;
static volatile       bit	INTF		@ ((unsigned)&INTCON*8)+1;
static volatile       bit	T0IF		@ ((unsigned)&INTCON*8)+2;
static                bit	RBIE		@ ((unsigned)&INTCON*8)+3;
// Alternate definition for backward compatibility
static                bit	RABIE		@ ((unsigned)&INTCON*8)+3;
static                bit	INTE		@ ((unsigned)&INTCON*8)+4;
static                bit	T0IE		@ ((unsigned)&INTCON*8)+5;
static                bit	PEIE		@ ((unsigned)&INTCON*8)+6;
static                bit	GIE		@ ((unsigned)&INTCON*8)+7;

/* Definitions for PIR1 register */
static volatile       bit	TMR1IF		@ ((unsigned)&PIR1*8)+0;
static volatile       bit	TMR2IF		@ ((unsigned)&PIR1*8)+1;
static volatile       bit	CCP1IF		@ ((unsigned)&PIR1*8)+2;
static volatile       bit	SSPIF		@ ((unsigned)&PIR1*8)+3;
static volatile       bit	TXIF		@ ((unsigned)&PIR1*8)+4;
static volatile       bit	RCIF		@ ((unsigned)&PIR1*8)+5;
static volatile       bit	ADIF		@ ((unsigned)&PIR1*8)+6;
static volatile       bit	EEIF		@ ((unsigned)&PIR1*8)+7;

/* Definitions for PIR2 register */
static volatile       bit	CCP2IF		@ ((unsigned)&PIR2*8)+0;
static volatile       bit	LVDIF		@ ((unsigned)&PIR2*8)+2;
static volatile       bit	LCDIF		@ ((unsigned)&PIR2*8)+4;
static volatile       bit	C1IF		@ ((unsigned)&PIR2*8)+5;
static volatile       bit	C2IF		@ ((unsigned)&PIR2*8)+6;
static volatile       bit	OSFIF		@ ((unsigned)&PIR2*8)+7;

/* Definitions for T1CON register */
static                bit	TMR1ON		@ ((unsigned)&T1CON*8)+0;
static                bit	TMR1CS		@ ((unsigned)&T1CON*8)+1;
static                bit	T1SYNC		@ ((unsigned)&T1CON*8)+2;
static                bit	T1OSCEN		@ ((unsigned)&T1CON*8)+3;
static                bit	T1CKPS0		@ ((unsigned)&T1CON*8)+4;
static                bit	T1CKPS1		@ ((unsigned)&T1CON*8)+5;
static                bit	T1GE		@ ((unsigned)&T1CON*8)+6;
static                bit	T1GINV		@ ((unsigned)&T1CON*8)+7;

/* Definitions for T2CON register */
static                bit	T2CKPS0		@ ((unsigned)&T2CON*8)+0;
static                bit	T2CKPS1		@ ((unsigned)&T2CON*8)+1;
static                bit	TMR2ON		@ ((unsigned)&T2CON*8)+2;
static                bit	TOUTPS0		@ ((unsigned)&T2CON*8)+3;
static                bit	TOUTPS1		@ ((unsigned)&T2CON*8)+4;
static                bit	TOUTPS2		@ ((unsigned)&T2CON*8)+5;
static                bit	TOUTPS3		@ ((unsigned)&T2CON*8)+6;

/* Definitions for SSPCON register */
static                bit	SSPM0		@ ((unsigned)&SSPCON*8)+0;
static                bit	SSPM1		@ ((unsigned)&SSPCON*8)+1;
static                bit	SSPM2		@ ((unsigned)&SSPCON*8)+2;
static                bit	SSPM3		@ ((unsigned)&SSPCON*8)+3;
static                bit	CKP		@ ((unsigned)&SSPCON*8)+4;
static                bit	SSPEN		@ ((unsigned)&SSPCON*8)+5;
static volatile       bit	SSPOV		@ ((unsigned)&SSPCON*8)+6;
static volatile       bit	WCOL		@ ((unsigned)&SSPCON*8)+7;

/* Definitions for CCP1CON register */
static                bit	CCP1M0		@ ((unsigned)&CCP1CON*8)+0;
static                bit	CCP1M1		@ ((unsigned)&CCP1CON*8)+1;
static                bit	CCP1M2		@ ((unsigned)&CCP1CON*8)+2;
static                bit	CCP1M3		@ ((unsigned)&CCP1CON*8)+3;
static volatile       bit	CCP1Y		@ ((unsigned)&CCP1CON*8)+4;
static volatile       bit	CCP1X		@ ((unsigned)&CCP1CON*8)+5;

/* Definitions for RCSTA register */
static volatile       bit	RX9D		@ ((unsigned)&RCSTA*8)+0;
static volatile       bit	OERR		@ ((unsigned)&RCSTA*8)+1;
static volatile       bit	FERR		@ ((unsigned)&RCSTA*8)+2;
static                bit	ADDEN		@ ((unsigned)&RCSTA*8)+3;
static                bit	CREN		@ ((unsigned)&RCSTA*8)+4;
static                bit	SREN		@ ((unsigned)&RCSTA*8)+5;
static                bit	RX9		@ ((unsigned)&RCSTA*8)+6;
static                bit	SPEN		@ ((unsigned)&RCSTA*8)+7;

/* Definitions for CCP2CON register */
static                bit	CCP2M0		@ ((unsigned)&CCP2CON*8)+0;
static                bit	CCP2M1		@ ((unsigned)&CCP2CON*8)+1;
static                bit	CCP2M2		@ ((unsigned)&CCP2CON*8)+2;
static                bit	CCP2M3		@ ((unsigned)&CCP2CON*8)+3;
static volatile       bit	CCP2Y		@ ((unsigned)&CCP2CON*8)+4;
static volatile       bit	CCP2X		@ ((unsigned)&CCP2CON*8)+5;

/* Definitions for ADCON0 register */
static                bit	ADON		@ ((unsigned)&ADCON0*8)+0;
static volatile       bit	GODONE		@ ((unsigned)&ADCON0*8)+1;
static                bit	CHS0		@ ((unsigned)&ADCON0*8)+2;
static                bit	CHS1		@ ((unsigned)&ADCON0*8)+3;
static                bit	CHS2		@ ((unsigned)&ADCON0*8)+4;
static                bit	VCFG0		@ ((unsigned)&ADCON0*8)+5;
static                bit	VCFG1		@ ((unsigned)&ADCON0*8)+6;
static                bit	ADFM		@ ((unsigned)&ADCON0*8)+7;

/* Definitions for OPTION register */
static          bank1 bit	PS0		@ ((unsigned)&OPTION*8)+0;
static          bank1 bit	PS1		@ ((unsigned)&OPTION*8)+1;
static          bank1 bit	PS2		@ ((unsigned)&OPTION*8)+2;
static          bank1 bit	PSA		@ ((unsigned)&OPTION*8)+3;
static          bank1 bit	T0SE		@ ((unsigned)&OPTION*8)+4;
static          bank1 bit	T0CS		@ ((unsigned)&OPTION*8)+5;
static          bank1 bit	INTEDG		@ ((unsigned)&OPTION*8)+6;
static          bank1 bit	RBPU		@ ((unsigned)&OPTION*8)+7;
// Alternate definition for backward compatibility
static          bank1 bit	RABPU		@ ((unsigned)&OPTION*8)+7;

/* Definitions for TRISA register */
static          bank1 bit	TRISA0		@ ((unsigned)&TRISA*8)+0;
static          bank1 bit	TRISA1		@ ((unsigned)&TRISA*8)+1;
static          bank1 bit	TRISA2		@ ((unsigned)&TRISA*8)+2;
static          bank1 bit	TRISA3		@ ((unsigned)&TRISA*8)+3;
static          bank1 bit	TRISA4		@ ((unsigned)&TRISA*8)+4;
static          bank1 bit	TRISA5		@ ((unsigned)&TRISA*8)+5;
static          bank1 bit	TRISA6		@ ((unsigned)&TRISA*8)+6;
static          bank1 bit	TRISA7		@ ((unsigned)&TRISA*8)+7;

/* Definitions for TRISB register */
static volatile bank1 bit	TRISB0		@ ((unsigned)&TRISB*8)+0;
static volatile bank1 bit	TRISB1		@ ((unsigned)&TRISB*8)+1;
static volatile bank1 bit	TRISB2		@ ((unsigned)&TRISB*8)+2;
static volatile bank1 bit	TRISB3		@ ((unsigned)&TRISB*8)+3;
static volatile bank1 bit	TRISB4		@ ((unsigned)&TRISB*8)+4;
static volatile bank1 bit	TRISB5		@ ((unsigned)&TRISB*8)+5;
static volatile bank1 bit	TRISB6		@ ((unsigned)&TRISB*8)+6;
static volatile bank1 bit	TRISB7		@ ((unsigned)&TRISB*8)+7;

/* Definitions for TRISC register */
static volatile bank1 bit	TRISC0		@ ((unsigned)&TRISC*8)+0;
static volatile bank1 bit	TRISC1		@ ((unsigned)&TRISC*8)+1;
static volatile bank1 bit	TRISC2		@ ((unsigned)&TRISC*8)+2;
static volatile bank1 bit	TRISC3		@ ((unsigned)&TRISC*8)+3;
static volatile bank1 bit	TRISC4		@ ((unsigned)&TRISC*8)+4;
static volatile bank1 bit	TRISC5		@ ((unsigned)&TRISC*8)+5;
static volatile bank1 bit	TRISC6		@ ((unsigned)&TRISC*8)+6;
static volatile bank1 bit	TRISC7		@ ((unsigned)&TRISC*8)+7;

/* Definitions for TRISD register */
static volatile bank1 bit	TRISD0		@ ((unsigned)&TRISD*8)+0;
static volatile bank1 bit	TRISD1		@ ((unsigned)&TRISD*8)+1;
static volatile bank1 bit	TRISD2		@ ((unsigned)&TRISD*8)+2;
static volatile bank1 bit	TRISD3		@ ((unsigned)&TRISD*8)+3;
static volatile bank1 bit	TRISD4		@ ((unsigned)&TRISD*8)+4;
static volatile bank1 bit	TRISD5		@ ((unsigned)&TRISD*8)+5;
static volatile bank1 bit	TRISD6		@ ((unsigned)&TRISD*8)+6;
static volatile bank1 bit	TRISD7		@ ((unsigned)&TRISD*8)+7;

/* Definitions for TRISE register */
static volatile bank1 bit	TRISE0		@ ((unsigned)&TRISE*8)+0;
static volatile bank1 bit	TRISE1		@ ((unsigned)&TRISE*8)+1;
static volatile bank1 bit	TRISE2		@ ((unsigned)&TRISE*8)+2;
static volatile bank1 bit	TRISE3		@ ((unsigned)&TRISE*8)+3;
static volatile bank1 bit	TRISE4		@ ((unsigned)&TRISE*8)+4;
static volatile bank1 bit	TRISE5		@ ((unsigned)&TRISE*8)+5;
static volatile bank1 bit	TRISE6		@ ((unsigned)&TRISE*8)+6;
static volatile bank1 bit	TRISE7		@ ((unsigned)&TRISE*8)+7;

/* Definitions for PIE1 register */
static          bank1 bit	TMR1IE		@ ((unsigned)&PIE1*8)+0;
static          bank1 bit	TMR2IE		@ ((unsigned)&PIE1*8)+1;
static          bank1 bit	CCP1IE		@ ((unsigned)&PIE1*8)+2;
static          bank1 bit	SSPIE		@ ((unsigned)&PIE1*8)+3;
static          bank1 bit	TXIE		@ ((unsigned)&PIE1*8)+4;
static          bank1 bit	RCIE		@ ((unsigned)&PIE1*8)+5;
static          bank1 bit	ADIE		@ ((unsigned)&PIE1*8)+6;
static          bank1 bit	EEIE		@ ((unsigned)&PIE1*8)+7;

/* Definitions for PIE2 register */
static          bank1 bit	CCP2IE		@ ((unsigned)&PIE2*8)+0;
static          bank1 bit	LVDIE		@ ((unsigned)&PIE2*8)+2;
static          bank1 bit	LCDIE		@ ((unsigned)&PIE2*8)+4;
static          bank1 bit	C1IE		@ ((unsigned)&PIE2*8)+5;
static          bank1 bit	C2IE		@ ((unsigned)&PIE2*8)+6;
static          bank1 bit	OSFIE		@ ((unsigned)&PIE2*8)+7;

/* Definitions for PCON register */
static volatile bank1 bit	BOR		@ ((unsigned)&PCON*8)+0;
static volatile bank1 bit	POR		@ ((unsigned)&PCON*8)+1;
static          bank1 bit	SBOREN		@ ((unsigned)&PCON*8)+4;

/* Definitions for OSCCON register */
static          bank1 bit	SCS		@ ((unsigned)&OSCCON*8)+0;
static volatile bank1 bit	LTS		@ ((unsigned)&OSCCON*8)+1;
static volatile bank1 bit	HTS		@ ((unsigned)&OSCCON*8)+2;
static volatile bank1 bit	OSTS		@ ((unsigned)&OSCCON*8)+3;
static          bank1 bit	IRCF0		@ ((unsigned)&OSCCON*8)+4;
static          bank1 bit	IRCF1		@ ((unsigned)&OSCCON*8)+5;
static          bank1 bit	IRCF2		@ ((unsigned)&OSCCON*8)+6;

/* Definitions for OSCTUNE register */
static          bank1 bit	TUN0		@ ((unsigned)&OSCTUNE*8)+0;
static          bank1 bit	TUN1		@ ((unsigned)&OSCTUNE*8)+1;
static          bank1 bit	TUN2		@ ((unsigned)&OSCTUNE*8)+2;
static          bank1 bit	TUN3		@ ((unsigned)&OSCTUNE*8)+3;
static          bank1 bit	TUN4		@ ((unsigned)&OSCTUNE*8)+4;

/* Definitions for ANSEL register */
static          bank1 bit	ANS0		@ ((unsigned)&ANSEL*8)+0;
static          bank1 bit	ANS1		@ ((unsigned)&ANSEL*8)+1;
static          bank1 bit	ANS2		@ ((unsigned)&ANSEL*8)+2;
static          bank1 bit	ANS3		@ ((unsigned)&ANSEL*8)+3;
static          bank1 bit	ANS4		@ ((unsigned)&ANSEL*8)+4;
static          bank1 bit	ANS5		@ ((unsigned)&ANSEL*8)+5;
static          bank1 bit	ANS6		@ ((unsigned)&ANSEL*8)+6;
static          bank1 bit	ANS7		@ ((unsigned)&ANSEL*8)+7;

/* Definitions for SSPSTAT register */
static volatile bank1 bit	BF		@ ((unsigned)&SSPSTAT*8)+0;
static volatile bank1 bit	UA		@ ((unsigned)&SSPSTAT*8)+1;
static volatile bank1 bit	RW		@ ((unsigned)&SSPSTAT*8)+2;
static volatile bank1 bit	START		@ ((unsigned)&SSPSTAT*8)+3;
static volatile bank1 bit	STOP		@ ((unsigned)&SSPSTAT*8)+4;
static volatile bank1 bit	DA		@ ((unsigned)&SSPSTAT*8)+5;
static          bank1 bit	CKE		@ ((unsigned)&SSPSTAT*8)+6;
static          bank1 bit	SMP		@ ((unsigned)&SSPSTAT*8)+7;

/* Definitions for WPUB register */
static          bank1 bit	WPUB0		@ ((unsigned)&WPUB*8)+0;
static          bank1 bit	WPUB1		@ ((unsigned)&WPUB*8)+1;
static          bank1 bit	WPUB2		@ ((unsigned)&WPUB*8)+2;
static          bank1 bit	WPUB3		@ ((unsigned)&WPUB*8)+3;
static          bank1 bit	WPUB4		@ ((unsigned)&WPUB*8)+4;
static          bank1 bit	WPUB5		@ ((unsigned)&WPUB*8)+5;
static          bank1 bit	WPUB6		@ ((unsigned)&WPUB*8)+6;
static          bank1 bit	WPUB7		@ ((unsigned)&WPUB*8)+7;

/* Definitions for IOCB register */
static          bank1 bit	IOCB4		@ ((unsigned)&IOCB*8)+4;
static          bank1 bit	IOCB5		@ ((unsigned)&IOCB*8)+5;
static          bank1 bit	IOCB6		@ ((unsigned)&IOCB*8)+6;
static          bank1 bit	IOCB7		@ ((unsigned)&IOCB*8)+7;

/* Definitions for CMCON1 register */
static          bank1 bit	C2SYNC		@ ((unsigned)&CMCON1*8)+0;
static          bank1 bit	T1GSS		@ ((unsigned)&CMCON1*8)+1;

/* Definitions for TXSTA register */
static volatile bank1 bit	TX9D		@ ((unsigned)&TXSTA*8)+0;
static volatile bank1 bit	TRMT		@ ((unsigned)&TXSTA*8)+1;
static          bank1 bit	BRGH		@ ((unsigned)&TXSTA*8)+2;
static          bank1 bit	SYNC		@ ((unsigned)&TXSTA*8)+4;
static          bank1 bit	TXEN		@ ((unsigned)&TXSTA*8)+5;
static          bank1 bit	TX9		@ ((unsigned)&TXSTA*8)+6;
static          bank1 bit	CSRC		@ ((unsigned)&TXSTA*8)+7;

/* Definitions for SPBRG register */
static          bank1 bit	SPBRG0		@ ((unsigned)&SPBRG*8)+0;
static          bank1 bit	SPBRG1		@ ((unsigned)&SPBRG*8)+1;
static          bank1 bit	SPBRG2		@ ((unsigned)&SPBRG*8)+2;
static          bank1 bit	SPBRG3		@ ((unsigned)&SPBRG*8)+3;
static          bank1 bit	SPBRG4		@ ((unsigned)&SPBRG*8)+4;
static          bank1 bit	SPBRG5		@ ((unsigned)&SPBRG*8)+5;
static          bank1 bit	SPBRG6		@ ((unsigned)&SPBRG*8)+6;
static          bank1 bit	SPBRG7		@ ((unsigned)&SPBRG*8)+7;

/* Definitions for CMCON0 register */
static          bank1 bit	CM0		@ ((unsigned)&CMCON0*8)+0;
static          bank1 bit	CM1		@ ((unsigned)&CMCON0*8)+1;
static          bank1 bit	CM2		@ ((unsigned)&CMCON0*8)+2;
static          bank1 bit	CIS		@ ((unsigned)&CMCON0*8)+3;
static          bank1 bit	C1INV		@ ((unsigned)&CMCON0*8)+4;
static          bank1 bit	C2INV		@ ((unsigned)&CMCON0*8)+5;
static volatile bank1 bit	C1OUT		@ ((unsigned)&CMCON0*8)+6;
static volatile bank1 bit	C2OUT		@ ((unsigned)&CMCON0*8)+7;

/* Definitions for VRCON register */
static          bank1 bit	VR0		@ ((unsigned)&VRCON*8)+0;
static          bank1 bit	VR1		@ ((unsigned)&VRCON*8)+1;
static          bank1 bit	VR2		@ ((unsigned)&VRCON*8)+2;
static          bank1 bit	VR3		@ ((unsigned)&VRCON*8)+3;
static          bank1 bit	VRR		@ ((unsigned)&VRCON*8)+5;
static          bank1 bit	VREN		@ ((unsigned)&VRCON*8)+7;

/* Definitions for ADCON1 register */
static          bank1 bit	ADCS0		@ ((unsigned)&ADCON1*8)+4;
static          bank1 bit	ADCS1		@ ((unsigned)&ADCON1*8)+5;
static          bank1 bit	ADCS2		@ ((unsigned)&ADCON1*8)+6;

/* Definitions for WDTCON register */
static          bank2 bit	SWDTEN		@ ((unsigned)&WDTCON*8)+0;
static          bank2 bit	WDTPS0		@ ((unsigned)&WDTCON*8)+1;
static          bank2 bit	WDTPS1		@ ((unsigned)&WDTCON*8)+2;
static          bank2 bit	WDTPS2		@ ((unsigned)&WDTCON*8)+3;
static          bank2 bit	WDTPS3		@ ((unsigned)&WDTCON*8)+4;

/* Definitions for LCDCON register */
static          bank2 bit	LMUX0		@ ((unsigned)&LCDCON*8)+0;
static          bank2 bit	LMUX1		@ ((unsigned)&LCDCON*8)+1;
static          bank2 bit	CS0		@ ((unsigned)&LCDCON*8)+2;
static          bank2 bit	CS1		@ ((unsigned)&LCDCON*8)+3;
static          bank2 bit	VLCDEN		@ ((unsigned)&LCDCON*8)+4;
static volatile bank2 bit	WERR		@ ((unsigned)&LCDCON*8)+5;
static          bank2 bit	SLPEN		@ ((unsigned)&LCDCON*8)+6;
static          bank2 bit	LCDEN		@ ((unsigned)&LCDCON*8)+7;

/* Definitions for LCDPS register */
static          bank2 bit	LP0		@ ((unsigned)&LCDPS*8)+0;
static          bank2 bit	LP1		@ ((unsigned)&LCDPS*8)+1;
static          bank2 bit	LP2		@ ((unsigned)&LCDPS*8)+2;
static          bank2 bit	LP3		@ ((unsigned)&LCDPS*8)+3;
static volatile bank2 bit	WA		@ ((unsigned)&LCDPS*8)+4;
static volatile bank2 bit	LCDA		@ ((unsigned)&LCDPS*8)+5;
static          bank2 bit	BIASMD		@ ((unsigned)&LCDPS*8)+6;
static          bank2 bit	WFT		@ ((unsigned)&LCDPS*8)+7;

/* Definitions for LVDCON register */
static          bank2 bit	LVDL0		@ ((unsigned)&LVDCON*8)+0;
static          bank2 bit	LVDL1		@ ((unsigned)&LVDCON*8)+1;
static          bank2 bit	LVDL2		@ ((unsigned)&LVDCON*8)+2;
static          bank2 bit	LVDEN		@ ((unsigned)&LVDCON*8)+4;
static volatile bank2 bit	IRVST		@ ((unsigned)&LVDCON*8)+5;

/* Definitions for LCDDATA0 register */
static          bank2 bit	SEG0COM0	@ ((unsigned)&LCDDATA0*8)+0;
static          bank2 bit	SEG1COM0	@ ((unsigned)&LCDDATA0*8)+1;
static          bank2 bit	SEG2COM0	@ ((unsigned)&LCDDATA0*8)+2;
static          bank2 bit	SEG3COM0	@ ((unsigned)&LCDDATA0*8)+3;
static          bank2 bit	SEG4COM0	@ ((unsigned)&LCDDATA0*8)+4;
static          bank2 bit	SEG5COM0	@ ((unsigned)&LCDDATA0*8)+5;
static          bank2 bit	SEG6COM0	@ ((unsigned)&LCDDATA0*8)+6;
static          bank2 bit	SEG7COM0	@ ((unsigned)&LCDDATA0*8)+7;

/* Definitions for LCDDATA1 register */
static          bank2 bit	SEG8COM0	@ ((unsigned)&LCDDATA1*8)+0;
static          bank2 bit	SEG9COM0	@ ((unsigned)&LCDDATA1*8)+1;
static          bank2 bit	SEG10COM0	@ ((unsigned)&LCDDATA1*8)+2;
static          bank2 bit	SEG11COM0	@ ((unsigned)&LCDDATA1*8)+3;
static          bank2 bit	SEG12COM0	@ ((unsigned)&LCDDATA1*8)+4;
static          bank2 bit	SEG13COM0	@ ((unsigned)&LCDDATA1*8)+5;
static          bank2 bit	SEG14COM0	@ ((unsigned)&LCDDATA1*8)+6;
static          bank2 bit	SEG15COM0	@ ((unsigned)&LCDDATA1*8)+7;

/* Definitions for LCDDATA2 register */
static          bank2 bit	SEG16COM0	@ ((unsigned)&LCDDATA2*8)+0;
static          bank2 bit	SEG17COM0	@ ((unsigned)&LCDDATA2*8)+1;
static          bank2 bit	SEG18COM0	@ ((unsigned)&LCDDATA2*8)+2;
static          bank2 bit	SEG19COM0	@ ((unsigned)&LCDDATA2*8)+3;
static          bank2 bit	SEG20COM0	@ ((unsigned)&LCDDATA2*8)+4;
static          bank2 bit	SEG21COM0	@ ((unsigned)&LCDDATA2*8)+5;
static          bank2 bit	SEG22COM0	@ ((unsigned)&LCDDATA2*8)+6;
static          bank2 bit	SEG23COM0	@ ((unsigned)&LCDDATA2*8)+7;

/* Definitions for LCDDATA3 register */
static          bank2 bit	SEG0COM1	@ ((unsigned)&LCDDATA3*8)+0;
static          bank2 bit	SEG1COM1	@ ((unsigned)&LCDDATA3*8)+1;
static          bank2 bit	SEG2COM1	@ ((unsigned)&LCDDATA3*8)+2;
static          bank2 bit	SEG3COM1	@ ((unsigned)&LCDDATA3*8)+3;
static          bank2 bit	SEG4COM1	@ ((unsigned)&LCDDATA3*8)+4;
static          bank2 bit	SEG5COM1	@ ((unsigned)&LCDDATA3*8)+5;
static          bank2 bit	SEG6COM1	@ ((unsigned)&LCDDATA3*8)+6;
static          bank2 bit	SEG7COM1	@ ((unsigned)&LCDDATA3*8)+7;

/* Definitions for LCDDATA4 register */
static          bank2 bit	SEG8COM1	@ ((unsigned)&LCDDATA4*8)+0;
static          bank2 bit	SEG9COM1	@ ((unsigned)&LCDDATA4*8)+1;
static          bank2 bit	SEG10COM1	@ ((unsigned)&LCDDATA4*8)+2;
static          bank2 bit	SEG11COM1	@ ((unsigned)&LCDDATA4*8)+3;
static          bank2 bit	SEG12COM1	@ ((unsigned)&LCDDATA4*8)+4;
static          bank2 bit	SEG13COM1	@ ((unsigned)&LCDDATA4*8)+5;
static          bank2 bit	SEG14COM1	@ ((unsigned)&LCDDATA4*8)+6;
static          bank2 bit	SEG15COM1	@ ((unsigned)&LCDDATA4*8)+7;

/* Definitions for LCDDATA5 register */
static          bank2 bit	SEG16COM1	@ ((unsigned)&LCDDATA5*8)+0;
static          bank2 bit	SEG17COM1	@ ((unsigned)&LCDDATA5*8)+1;
static          bank2 bit	SEG18COM1	@ ((unsigned)&LCDDATA5*8)+2;
static          bank2 bit	SEG19COM1	@ ((unsigned)&LCDDATA5*8)+3;
static          bank2 bit	SEG20COM1	@ ((unsigned)&LCDDATA5*8)+4;
static          bank2 bit	SEG21COM1	@ ((unsigned)&LCDDATA5*8)+5;
static          bank2 bit	SEG22COM1	@ ((unsigned)&LCDDATA5*8)+6;
static          bank2 bit	SEG23COM1	@ ((unsigned)&LCDDATA5*8)+7;

/* Definitions for LCDDATA6 register */
static          bank2 bit	SEG0COM2	@ ((unsigned)&LCDDATA6*8)+0;
static          bank2 bit	SEG1COM2	@ ((unsigned)&LCDDATA6*8)+1;
static          bank2 bit	SEG2COM2	@ ((unsigned)&LCDDATA6*8)+2;
static          bank2 bit	SEG3COM2	@ ((unsigned)&LCDDATA6*8)+3;
static          bank2 bit	SEG4COM2	@ ((unsigned)&LCDDATA6*8)+4;
static          bank2 bit	SEG5COM2	@ ((unsigned)&LCDDATA6*8)+5;
static          bank2 bit	SEG6COM2	@ ((unsigned)&LCDDATA6*8)+6;
static          bank2 bit	SEG7COM2	@ ((unsigned)&LCDDATA6*8)+7;

/* Definitions for LCDDATA7 register */
static          bank2 bit	SEG8COM2	@ ((unsigned)&LCDDATA7*8)+0;
static          bank2 bit	SEG9COM2	@ ((unsigned)&LCDDATA7*8)+1;
static          bank2 bit	SEG10COM2	@ ((unsigned)&LCDDATA7*8)+2;
static          bank2 bit	SEG11COM2	@ ((unsigned)&LCDDATA7*8)+3;
static          bank2 bit	SEG12COM2	@ ((unsigned)&LCDDATA7*8)+4;
static          bank2 bit	SEG13COM2	@ ((unsigned)&LCDDATA7*8)+5;
static          bank2 bit	SEG14COM2	@ ((unsigned)&LCDDATA7*8)+6;
static          bank2 bit	SEG15COM2	@ ((unsigned)&LCDDATA7*8)+7;

/* Definitions for LCDDATA8 register */
static          bank2 bit	SEG16COM2	@ ((unsigned)&LCDDATA8*8)+0;
static          bank2 bit	SEG17COM2	@ ((unsigned)&LCDDATA8*8)+1;
static          bank2 bit	SEG18COM2	@ ((unsigned)&LCDDATA8*8)+2;
static          bank2 bit	SEG19COM2	@ ((unsigned)&LCDDATA8*8)+3;
static          bank2 bit	SEG20COM2	@ ((unsigned)&LCDDATA8*8)+4;
static          bank2 bit	SEG21COM2	@ ((unsigned)&LCDDATA8*8)+5;
static          bank2 bit	SEG22COM2	@ ((unsigned)&LCDDATA8*8)+6;
static          bank2 bit	SEG23COM2	@ ((unsigned)&LCDDATA8*8)+7;

/* Definitions for LCDDATA9 register */
static          bank2 bit	SEG0COM3	@ ((unsigned)&LCDDATA9*8)+0;
static          bank2 bit	SEG1COM3	@ ((unsigned)&LCDDATA9*8)+1;
static          bank2 bit	SEG2COM3	@ ((unsigned)&LCDDATA9*8)+2;
static          bank2 bit	SEG3COM3	@ ((unsigned)&LCDDATA9*8)+3;
static          bank2 bit	SEG4COM3	@ ((unsigned)&LCDDATA9*8)+4;
static          bank2 bit	SEG5COM3	@ ((unsigned)&LCDDATA9*8)+5;
static          bank2 bit	SEG6COM3	@ ((unsigned)&LCDDATA9*8)+6;
static          bank2 bit	SEG7COM3	@ ((unsigned)&LCDDATA9*8)+7;

/* Definitions for LCDDATA10 register */
static          bank2 bit	SEG8COM3	@ ((unsigned)&LCDDATA10*8)+0;
static          bank2 bit	SEG9COM3	@ ((unsigned)&LCDDATA10*8)+1;
static          bank2 bit	SEG10COM3	@ ((unsigned)&LCDDATA10*8)+2;
static          bank2 bit	SEG11COM3	@ ((unsigned)&LCDDATA10*8)+3;
static          bank2 bit	SEG12COM3	@ ((unsigned)&LCDDATA10*8)+4;
static          bank2 bit	SEG13COM3	@ ((unsigned)&LCDDATA10*8)+5;
static          bank2 bit	SEG14COM3	@ ((unsigned)&LCDDATA10*8)+6;
static          bank2 bit	SEG15COM3	@ ((unsigned)&LCDDATA10*8)+7;

/* Definitions for LCDDATA11 register */
static          bank2 bit	SEG16COM3	@ ((unsigned)&LCDDATA11*8)+0;
static          bank2 bit	SEG17COM3	@ ((unsigned)&LCDDATA11*8)+1;
static          bank2 bit	SEG18COM3	@ ((unsigned)&LCDDATA11*8)+2;
static          bank2 bit	SEG19COM3	@ ((unsigned)&LCDDATA11*8)+3;
static          bank2 bit	SEG20COM3	@ ((unsigned)&LCDDATA11*8)+4;
static          bank2 bit	SEG21COM3	@ ((unsigned)&LCDDATA11*8)+5;
static          bank2 bit	SEG22COM3	@ ((unsigned)&LCDDATA11*8)+6;
static          bank2 bit	SEG23COM3	@ ((unsigned)&LCDDATA11*8)+7;

/* Definitions for LCDSE0 register */
static          bank2 bit	SE0		@ ((unsigned)&LCDSE0*8)+0;
static          bank2 bit	SE1		@ ((unsigned)&LCDSE0*8)+1;
static          bank2 bit	SE2		@ ((unsigned)&LCDSE0*8)+2;
static          bank2 bit	SE3		@ ((unsigned)&LCDSE0*8)+3;
static          bank2 bit	SE4		@ ((unsigned)&LCDSE0*8)+4;
static          bank2 bit	SE5		@ ((unsigned)&LCDSE0*8)+5;
static          bank2 bit	SE6		@ ((unsigned)&LCDSE0*8)+6;
static          bank2 bit	SE7		@ ((unsigned)&LCDSE0*8)+7;

/* Definitions for LCDSE1 register */
static          bank2 bit	SE8		@ ((unsigned)&LCDSE1*8)+0;
static          bank2 bit	SE9		@ ((unsigned)&LCDSE1*8)+1;
static          bank2 bit	SE10		@ ((unsigned)&LCDSE1*8)+2;
static          bank2 bit	SE11		@ ((unsigned)&LCDSE1*8)+3;
static          bank2 bit	SE12		@ ((unsigned)&LCDSE1*8)+4;
static          bank2 bit	SE13		@ ((unsigned)&LCDSE1*8)+5;
static          bank2 bit	SE14		@ ((unsigned)&LCDSE1*8)+6;
static          bank2 bit	SE15		@ ((unsigned)&LCDSE1*8)+7;

/* Definitions for LCDSE2 register */
static          bank2 bit	SE16		@ ((unsigned)&LCDSE2*8)+0;
static          bank2 bit	SE17		@ ((unsigned)&LCDSE2*8)+1;
static          bank2 bit	SE18		@ ((unsigned)&LCDSE2*8)+2;
static          bank2 bit	SE19		@ ((unsigned)&LCDSE2*8)+3;
static          bank2 bit	SE20		@ ((unsigned)&LCDSE2*8)+4;
static          bank2 bit	SE21		@ ((unsigned)&LCDSE2*8)+5;
static          bank2 bit	SE22		@ ((unsigned)&LCDSE2*8)+6;
static          bank2 bit	SE23		@ ((unsigned)&LCDSE2*8)+7;

/* Definitions for TRISF register */
static volatile bank3 bit	TRISF0		@ ((unsigned)&TRISF*8)+0;
static volatile bank3 bit	TRISF1		@ ((unsigned)&TRISF*8)+1;
static volatile bank3 bit	TRISF2		@ ((unsigned)&TRISF*8)+2;
static volatile bank3 bit	TRISF3		@ ((unsigned)&TRISF*8)+3;
static volatile bank3 bit	TRISF4		@ ((unsigned)&TRISF*8)+4;
static volatile bank3 bit	TRISF5		@ ((unsigned)&TRISF*8)+5;
static volatile bank3 bit	TRISF6		@ ((unsigned)&TRISF*8)+6;
static volatile bank3 bit	TRISF7		@ ((unsigned)&TRISF*8)+7;

/* Definitions for TRISG register */
static volatile bank3 bit	TRISG0		@ ((unsigned)&TRISG*8)+0;
static volatile bank3 bit	TRISG1		@ ((unsigned)&TRISG*8)+1;
static volatile bank3 bit	TRISG2		@ ((unsigned)&TRISG*8)+2;
static volatile bank3 bit	TRISG3		@ ((unsigned)&TRISG*8)+3;
static volatile bank3 bit	TRISG4		@ ((unsigned)&TRISG*8)+4;
static volatile bank3 bit	TRISG5		@ ((unsigned)&TRISG*8)+5;

/* Definitions for PORTF register */
static volatile bank3 bit	RF0		@ ((unsigned)&PORTF*8)+0;
static volatile bank3 bit	RF1		@ ((unsigned)&PORTF*8)+1;
static volatile bank3 bit	RF2		@ ((unsigned)&PORTF*8)+2;
static volatile bank3 bit	RF3		@ ((unsigned)&PORTF*8)+3;
static volatile bank3 bit	RF4		@ ((unsigned)&PORTF*8)+4;
static volatile bank3 bit	RF5		@ ((unsigned)&PORTF*8)+5;
static volatile bank3 bit	RF6		@ ((unsigned)&PORTF*8)+6;
static volatile bank3 bit	RF7		@ ((unsigned)&PORTF*8)+7;

/* Definitions for PORTG register */
static volatile bank3 bit	RG0		@ ((unsigned)&PORTG*8)+0;
static volatile bank3 bit	RG1		@ ((unsigned)&PORTG*8)+1;
static volatile bank3 bit	RG2		@ ((unsigned)&PORTG*8)+2;
static volatile bank3 bit	RG3		@ ((unsigned)&PORTG*8)+3;
static volatile bank3 bit	RG4		@ ((unsigned)&PORTG*8)+4;
static volatile bank3 bit	RG5		@ ((unsigned)&PORTG*8)+5;

/* Definitions for EECON1 register */
static volatile bank3 bit	RD		@ ((unsigned)&EECON1*8)+0;
static volatile bank3 bit	WR		@ ((unsigned)&EECON1*8)+1;
static          bank3 bit	WREN		@ ((unsigned)&EECON1*8)+2;
static volatile bank3 bit	WRERR		@ ((unsigned)&EECON1*8)+3;
static          bank3 bit	EEPGD		@ ((unsigned)&EECON1*8)+7;

/* Definitions for LCDDATA12 register */
static          bank3 bit	SEG24COM0	@ ((unsigned)&LCDDATA12*8)+0;
static          bank3 bit	SEG25COM0	@ ((unsigned)&LCDDATA12*8)+1;
static          bank3 bit	SEG26COM0	@ ((unsigned)&LCDDATA12*8)+2;
static          bank3 bit	SEG27COM0	@ ((unsigned)&LCDDATA12*8)+3;
static          bank3 bit	SEG28COM0	@ ((unsigned)&LCDDATA12*8)+4;
static          bank3 bit	SEG29COM0	@ ((unsigned)&LCDDATA12*8)+5;
static          bank3 bit	SEG30COM0	@ ((unsigned)&LCDDATA12*8)+6;
static          bank3 bit	SEG31COM0	@ ((unsigned)&LCDDATA12*8)+7;

/* Definitions for LCDDATA13 register */
static          bank3 bit	SEG32COM0	@ ((unsigned)&LCDDATA13*8)+0;
static          bank3 bit	SEG33COM0	@ ((unsigned)&LCDDATA13*8)+1;
static          bank3 bit	SEG34COM0	@ ((unsigned)&LCDDATA13*8)+2;
static          bank3 bit	SEG35COM0	@ ((unsigned)&LCDDATA13*8)+3;
static          bank3 bit	SEG36COM0	@ ((unsigned)&LCDDATA13*8)+4;
static          bank3 bit	SEG37COM0	@ ((unsigned)&LCDDATA13*8)+5;
static          bank3 bit	SEG38COM0	@ ((unsigned)&LCDDATA13*8)+6;
static          bank3 bit	SEG39COM0	@ ((unsigned)&LCDDATA13*8)+7;

/* Definitions for LCDDATA14 register */
static          bank3 bit	SEG40COM0	@ ((unsigned)&LCDDATA14*8)+0;
static          bank3 bit	SEG41COM0	@ ((unsigned)&LCDDATA14*8)+1;

/* Definitions for LCDDATA15 register */
static          bank3 bit	SEG24COM1	@ ((unsigned)&LCDDATA15*8)+0;
static          bank3 bit	SEG25COM1	@ ((unsigned)&LCDDATA15*8)+1;
static          bank3 bit	SEG26COM1	@ ((unsigned)&LCDDATA15*8)+2;
static          bank3 bit	SEG27COM1	@ ((unsigned)&LCDDATA15*8)+3;
static          bank3 bit	SEG28COM1	@ ((unsigned)&LCDDATA15*8)+4;
static          bank3 bit	SEG29COM1	@ ((unsigned)&LCDDATA15*8)+5;
static          bank3 bit	SEG30COM1	@ ((unsigned)&LCDDATA15*8)+6;
static          bank3 bit	SEG31COM1	@ ((unsigned)&LCDDATA15*8)+7;

/* Definitions for LCDDATA16 register */
static          bank3 bit	SEG32COM1	@ ((unsigned)&LCDDATA16*8)+0;
static          bank3 bit	SEG33COM1	@ ((unsigned)&LCDDATA16*8)+1;
static          bank3 bit	SEG34COM1	@ ((unsigned)&LCDDATA16*8)+2;
static          bank3 bit	SEG35COM1	@ ((unsigned)&LCDDATA16*8)+3;
static          bank3 bit	SEG36COM1	@ ((unsigned)&LCDDATA16*8)+4;
static          bank3 bit	SEG37COM1	@ ((unsigned)&LCDDATA16*8)+5;
static          bank3 bit	SEG38COM1	@ ((unsigned)&LCDDATA16*8)+6;
static          bank3 bit	SEG39COM1	@ ((unsigned)&LCDDATA16*8)+7;

/* Definitions for LCDDATA17 register */
static          bank3 bit	SEG40COM1	@ ((unsigned)&LCDDATA17*8)+0;
static          bank3 bit	SEG41COM1	@ ((unsigned)&LCDDATA17*8)+1;

/* Definitions for LCDDATA18 register */
static          bank3 bit	SEG24COM2	@ ((unsigned)&LCDDATA18*8)+0;
static          bank3 bit	SEG25COM2	@ ((unsigned)&LCDDATA18*8)+1;
static          bank3 bit	SEG26COM2	@ ((unsigned)&LCDDATA18*8)+2;
static          bank3 bit	SEG27COM2	@ ((unsigned)&LCDDATA18*8)+3;
static          bank3 bit	SEG28COM2	@ ((unsigned)&LCDDATA18*8)+4;
static          bank3 bit	SEG29COM2	@ ((unsigned)&LCDDATA18*8)+5;
static          bank3 bit	SEG30COM2	@ ((unsigned)&LCDDATA18*8)+6;
static          bank3 bit	SEG31COM2	@ ((unsigned)&LCDDATA18*8)+7;

/* Definitions for LCDDATA19 register */
static          bank3 bit	SEG32COM2	@ ((unsigned)&LCDDATA19*8)+0;
static          bank3 bit	SEG33COM2	@ ((unsigned)&LCDDATA19*8)+1;
static          bank3 bit	SEG34COM2	@ ((unsigned)&LCDDATA19*8)+2;
static          bank3 bit	SEG35COM2	@ ((unsigned)&LCDDATA19*8)+3;
static          bank3 bit	SEG36COM2	@ ((unsigned)&LCDDATA19*8)+4;
static          bank3 bit	SEG37COM2	@ ((unsigned)&LCDDATA19*8)+5;
static          bank3 bit	SEG38COM2	@ ((unsigned)&LCDDATA19*8)+6;
static          bank3 bit	SEG39COM2	@ ((unsigned)&LCDDATA19*8)+7;

/* Definitions for LCDDATA20 register */
static          bank3 bit	SEG40COM2	@ ((unsigned)&LCDDATA20*8)+0;
static          bank3 bit	SEG41COM2	@ ((unsigned)&LCDDATA20*8)+1;

/* Definitions for LCDDATA21 register */
static          bank3 bit	SEG24COM3	@ ((unsigned)&LCDDATA21*8)+0;
static          bank3 bit	SEG25COM3	@ ((unsigned)&LCDDATA21*8)+1;
static          bank3 bit	SEG26COM3	@ ((unsigned)&LCDDATA21*8)+2;
static          bank3 bit	SEG27COM3	@ ((unsigned)&LCDDATA21*8)+3;
static          bank3 bit	SEG28COM3	@ ((unsigned)&LCDDATA21*8)+4;
static          bank3 bit	SEG29COM3	@ ((unsigned)&LCDDATA21*8)+5;
static          bank3 bit	SEG30COM3	@ ((unsigned)&LCDDATA21*8)+6;
static          bank3 bit	SEG31COM3	@ ((unsigned)&LCDDATA21*8)+7;

/* Definitions for LCDDATA22 register */
static          bank3 bit	SEG32COM3	@ ((unsigned)&LCDDATA22*8)+0;
static          bank3 bit	SEG33COM3	@ ((unsigned)&LCDDATA22*8)+1;
static          bank3 bit	SEG34COM3	@ ((unsigned)&LCDDATA22*8)+2;
static          bank3 bit	SEG35COM3	@ ((unsigned)&LCDDATA22*8)+3;
static          bank3 bit	SEG36COM3	@ ((unsigned)&LCDDATA22*8)+4;
static          bank3 bit	SEG37COM3	@ ((unsigned)&LCDDATA22*8)+5;
static          bank3 bit	SEG38COM3	@ ((unsigned)&LCDDATA22*8)+6;
static          bank3 bit	SEG39COM3	@ ((unsigned)&LCDDATA22*8)+7;

/* Definitions for LCDDATA23 register */
static          bank3 bit	SEG40COM3	@ ((unsigned)&LCDDATA23*8)+0;
static          bank3 bit	SEG41COM3	@ ((unsigned)&LCDDATA23*8)+1;

/* Definitions for LCDSE3 register */
static          bank3 bit	SE24		@ ((unsigned)&LCDSE3*8)+0;
static          bank3 bit	SE25		@ ((unsigned)&LCDSE3*8)+1;
static          bank3 bit	SE26		@ ((unsigned)&LCDSE3*8)+2;
static          bank3 bit	SE27		@ ((unsigned)&LCDSE3*8)+3;
static          bank3 bit	SE28		@ ((unsigned)&LCDSE3*8)+4;
static          bank3 bit	SE29		@ ((unsigned)&LCDSE3*8)+5;
static          bank3 bit	SE30		@ ((unsigned)&LCDSE3*8)+6;
static          bank3 bit	SE31		@ ((unsigned)&LCDSE3*8)+7;

/* Definitions for LCDSE4 register */
static          bank3 bit	SE32		@ ((unsigned)&LCDSE4*8)+0;
static          bank3 bit	SE33		@ ((unsigned)&LCDSE4*8)+1;
static          bank3 bit	SE34		@ ((unsigned)&LCDSE4*8)+2;
static          bank3 bit	SE35		@ ((unsigned)&LCDSE4*8)+3;
static          bank3 bit	SE36		@ ((unsigned)&LCDSE4*8)+4;
static          bank3 bit	SE37		@ ((unsigned)&LCDSE4*8)+5;
static          bank3 bit	SE38		@ ((unsigned)&LCDSE4*8)+6;
static          bank3 bit	SE39		@ ((unsigned)&LCDSE4*8)+7;

/* Definitions for LCDSE5 register */
static          bank3 bit	SE40		@ ((unsigned)&LCDSE5*8)+0;
static          bank3 bit	SE41		@ ((unsigned)&LCDSE5*8)+1;

// Configuration Mask Definitions
#define CONFIG_ADDR	0x2007
// Oscillator 
#define EXTCLK		0x3FFF	// External RC Clockout
#define EXTIO		0x3FFE	// External RC No Clock
#define INTCLK		0x3FFD	// Internal RC Clockout
#define INTIO		0x3FFC	// Internal RC No Clock
#define EC		0x3FFB	// EC
#define HS		0x3FFA	// HS
#define XT		0x3FF9	// XT
#define LP		0x3FF8	// LP
// Watchdog Timer 
#define WDTEN		0x3FFF	// On
#define WDTDIS		0x3FF7	// Disabled / SWDTEN control
// Power Up Timer 
#define PWRTDIS		0x3FFF	// Off
#define PWRTEN		0x3FEF	// On
// Master Clear Enable 
#define MCLREN		0x3FFF	// MCLR function is enabled
#define MCLRDIS		0x3FDF	// MCLR functions as IO
// Code Protect 
#define UNPROTECT	0x3FFF	// Code is not protected
#define CP		0x3FBF	// Code is protected
// Data EE Read Protect 
#define DUNPROTECT	0x3FFF	// Do not read protect EEPROM data
#define CPD		0x3F7F	// Read protect EEPROM data
// Brown Out Detect 
#define BORDIS		0x3CFF	// BOD and SBOREN disabled
#define SWBOREN		0x3DFF	// SBOREN controls BOR function (Software control)
#define BORXSLP		0x3EFF	// BOD enabled in run, disabled in sleep, SBOREN disabled
#define BOREN		0x3FFF	// BOD Enabled, SBOREN Disabled
// Internal External Switch Over Mode 
#define IESOEN		0x3FFF	// Enabled
#define IESODIS		0x3BFF	// Disabled
// Monitor Clock Fail-safe 
#define FCMEN		0x3FFF	// Enabled
#define FCMDIS		0x37FF	// Disabled
// In-Circuit Debugger Mode
#define DEBUGEN		0x2FFF	// Enable ICD2 debugging
#define DEBUGDIS	0x3FFF	// Disable ICD2 debugging

#endif
