
#ifndef	_HTC_H_
#warning Header file pic16f616.h included directly. Use #include <htc.h> instead.
#endif

 /* header file for the MICROCHIP PIC microcontroller
	16F616
	16HV616
 */

#ifndef	__PIC16F616_H
#define	__PIC16F616_H

// Special function register definitions

static volatile       unsigned char	TMR0		@ 0x001;
static volatile       unsigned char	PCL		@ 0x002;
static volatile       unsigned char	STATUS		@ 0x003;
static                unsigned char	FSR		@ 0x004;
static volatile       unsigned char	PORTA		@ 0x005;
static volatile       unsigned char	PORTC		@ 0x007;
static volatile       unsigned char	PCLATH		@ 0x00A;
static volatile       unsigned char	INTCON		@ 0x00B;
static volatile       unsigned char	PIR1		@ 0x00C;
static volatile       unsigned char	TMR1L		@ 0x00E;
static volatile       unsigned char	TMR1H		@ 0x00F;
static                unsigned char	T1CON		@ 0x010;
static volatile       unsigned char	TMR2		@ 0x011;
static                unsigned char	T2CON		@ 0x012;
static volatile       unsigned char	CCPR1L		@ 0x013;
static volatile       unsigned char	CCPR1H		@ 0x014;
static volatile       unsigned char	CCP1CON		@ 0x015;
static volatile       unsigned char	PWM1CON		@ 0x016;
static volatile       unsigned char	ECCPAS		@ 0x017;
static                unsigned char	VRCON		@ 0x019;
static volatile       unsigned char	CM1CON0		@ 0x01A;
static volatile       unsigned char	CM2CON0		@ 0x01B;
static volatile       unsigned char	CM2CON1		@ 0x01C;
static volatile       unsigned char	ADRESH		@ 0x01E;
static volatile       unsigned char	ADCON0		@ 0x01F;
static          bank1 unsigned char	OPTION		@ 0x081;
static volatile bank1 unsigned char	TRISA		@ 0x085;
static volatile bank1 unsigned char	TRISC		@ 0x087;
static          bank1 unsigned char	PIE1		@ 0x08C;
static volatile bank1 unsigned char	PCON		@ 0x08E;
static          bank1 unsigned char	OSCTUNE		@ 0x090;
static          bank1 unsigned char	ANSEL		@ 0x091;
static          bank1 unsigned char	PR2		@ 0x092;
static          bank1 unsigned char	WPUA		@ 0x095;
static          bank1 unsigned char	IOCA		@ 0x096;
static volatile bank1 unsigned char	SRCON0		@ 0x099;
static          bank1 unsigned char	SRCON1		@ 0x09A;
static volatile bank1 unsigned char	ADRESL		@ 0x09E;
static          bank1 unsigned char	ADCON1		@ 0x09F;


/* Definitions for STATUS register */
static volatile       bit	CARRY		@ ((unsigned)&STATUS*8)+0;
static volatile       bit	DC		@ ((unsigned)&STATUS*8)+1;
static volatile       bit	ZERO		@ ((unsigned)&STATUS*8)+2;
static volatile       bit	PD		@ ((unsigned)&STATUS*8)+3;
static volatile       bit	TO		@ ((unsigned)&STATUS*8)+4;
static                bit	RP0		@ ((unsigned)&STATUS*8)+5;
static                bit	RP1		@ ((unsigned)&STATUS*8)+6;
static                bit	IRP		@ ((unsigned)&STATUS*8)+7;

/* Definitions for PORTA register */
static volatile       bit	RA0		@ ((unsigned)&PORTA*8)+0;
static volatile       bit	RA1		@ ((unsigned)&PORTA*8)+1;
static volatile       bit	RA2		@ ((unsigned)&PORTA*8)+2;
static volatile       bit	RA3		@ ((unsigned)&PORTA*8)+3;
static volatile       bit	RA4		@ ((unsigned)&PORTA*8)+4;
static volatile       bit	RA5		@ ((unsigned)&PORTA*8)+5;

/* Definitions for PORTC register */
static volatile       bit	RC0		@ ((unsigned)&PORTC*8)+0;
static volatile       bit	RC1		@ ((unsigned)&PORTC*8)+1;
static volatile       bit	RC2		@ ((unsigned)&PORTC*8)+2;
static volatile       bit	RC3		@ ((unsigned)&PORTC*8)+3;
static volatile       bit	RC4		@ ((unsigned)&PORTC*8)+4;
static volatile       bit	RC5		@ ((unsigned)&PORTC*8)+5;

/* Definitions for INTCON register */
static volatile       bit	RAIF		@ ((unsigned)&INTCON*8)+0;
static volatile       bit	INTF		@ ((unsigned)&INTCON*8)+1;
static volatile       bit	T0IF		@ ((unsigned)&INTCON*8)+2;
static                bit	RAIE		@ ((unsigned)&INTCON*8)+3;
static                bit	INTE		@ ((unsigned)&INTCON*8)+4;
static                bit	T0IE		@ ((unsigned)&INTCON*8)+5;
static                bit	PEIE		@ ((unsigned)&INTCON*8)+6;
static                bit	GIE		@ ((unsigned)&INTCON*8)+7;

/* Definitions for PIR1 register */
static volatile       bit	TMR1IF		@ ((unsigned)&PIR1*8)+0;
static volatile       bit	TMR2IF		@ ((unsigned)&PIR1*8)+1;
static volatile       bit	C1IF		@ ((unsigned)&PIR1*8)+3;
static volatile       bit	C2IF		@ ((unsigned)&PIR1*8)+4;
static volatile       bit	CCP1IF		@ ((unsigned)&PIR1*8)+5;
static volatile       bit	ADIF		@ ((unsigned)&PIR1*8)+6;

/* Definitions for T1CON register */
static                bit	TMR1ON		@ ((unsigned)&T1CON*8)+0;
static                bit	TMR1CS		@ ((unsigned)&T1CON*8)+1;
static                bit	T1SYNC		@ ((unsigned)&T1CON*8)+2;
static                bit	T1OSCEN		@ ((unsigned)&T1CON*8)+3;
static                bit	T1CKPS0		@ ((unsigned)&T1CON*8)+4;
static                bit	T1CKPS1		@ ((unsigned)&T1CON*8)+5;
static                bit	TMR1GE		@ ((unsigned)&T1CON*8)+6;
static                bit	T1GINV		@ ((unsigned)&T1CON*8)+7;

/* Definitions for T2CON register */
static                bit	T2CKPS0		@ ((unsigned)&T2CON*8)+0;
static                bit	T2CKPS1		@ ((unsigned)&T2CON*8)+1;
static                bit	TMR2ON		@ ((unsigned)&T2CON*8)+2;
static                bit	TOUTPS0		@ ((unsigned)&T2CON*8)+3;
static                bit	TOUTPS1		@ ((unsigned)&T2CON*8)+4;
static                bit	TOUTPS2		@ ((unsigned)&T2CON*8)+5;
static                bit	TOUTPS3		@ ((unsigned)&T2CON*8)+6;

/* Definitions for CCP1CON register */
static                bit	CCP1M0		@ ((unsigned)&CCP1CON*8)+0;
static                bit	CCP1M1		@ ((unsigned)&CCP1CON*8)+1;
static                bit	CCP1M2		@ ((unsigned)&CCP1CON*8)+2;
static                bit	CCP1M3		@ ((unsigned)&CCP1CON*8)+3;
static                bit	DC1B0		@ ((unsigned)&CCP1CON*8)+4;
static                bit	DC1B1		@ ((unsigned)&CCP1CON*8)+5;
static                bit	P1M0		@ ((unsigned)&CCP1CON*8)+6;
static                bit	P1M1		@ ((unsigned)&CCP1CON*8)+7;

/* Definitions for PWM1CON register */
static volatile       bit	PDC0		@ ((unsigned)&PWM1CON*8)+0;
static volatile       bit	PDC1		@ ((unsigned)&PWM1CON*8)+1;
static volatile       bit	PDC2		@ ((unsigned)&PWM1CON*8)+2;
static volatile       bit	PDC3		@ ((unsigned)&PWM1CON*8)+3;
static volatile       bit	PDC4		@ ((unsigned)&PWM1CON*8)+4;
static volatile       bit	PDC5		@ ((unsigned)&PWM1CON*8)+5;
static volatile       bit	PDC6		@ ((unsigned)&PWM1CON*8)+6;
static volatile       bit	PRSEN		@ ((unsigned)&PWM1CON*8)+7;

/* Definitions for ECCPAS register */
static                bit	PSSBD0		@ ((unsigned)&ECCPAS*8)+0;
static                bit	PSSBD1		@ ((unsigned)&ECCPAS*8)+1;
static                bit	PSSAC0		@ ((unsigned)&ECCPAS*8)+2;
static                bit	PSSAC1		@ ((unsigned)&ECCPAS*8)+3;
static                bit	ECCPAS0		@ ((unsigned)&ECCPAS*8)+4;
static                bit	ECCPAS1		@ ((unsigned)&ECCPAS*8)+5;
static                bit	ECCPAS2		@ ((unsigned)&ECCPAS*8)+6;
static volatile       bit	ECCPASE		@ ((unsigned)&ECCPAS*8)+7;

/* Definitions for VRCON register */
static                bit	VR0		@ ((unsigned)&VRCON*8)+0;
static                bit	VR1		@ ((unsigned)&VRCON*8)+1;
static                bit	VR2		@ ((unsigned)&VRCON*8)+2;
static                bit	VR3		@ ((unsigned)&VRCON*8)+3;
static                bit	VP6EN		@ ((unsigned)&VRCON*8)+4;
static                bit	VRR		@ ((unsigned)&VRCON*8)+5;
static                bit	C2VREN		@ ((unsigned)&VRCON*8)+6;
static                bit	C1VREN		@ ((unsigned)&VRCON*8)+7;

/* Definitions for CM1CON0 register */
static                bit	C1CH0		@ ((unsigned)&CM1CON0*8)+0;
static                bit	C1CH1		@ ((unsigned)&CM1CON0*8)+1;
static                bit	C1R		@ ((unsigned)&CM1CON0*8)+2;
static                bit	C1POL		@ ((unsigned)&CM1CON0*8)+4;
static                bit	C1OE		@ ((unsigned)&CM1CON0*8)+5;
static volatile       bit	C1OUT		@ ((unsigned)&CM1CON0*8)+6;
static                bit	C1ON		@ ((unsigned)&CM1CON0*8)+7;

/* Definitions for CM2CON0 register */
static                bit	C2CH0		@ ((unsigned)&CM2CON0*8)+0;
static                bit	C2CH1		@ ((unsigned)&CM2CON0*8)+1;
static                bit	C2R		@ ((unsigned)&CM2CON0*8)+2;
static                bit	C2POL		@ ((unsigned)&CM2CON0*8)+4;
static                bit	C2OE		@ ((unsigned)&CM2CON0*8)+5;
static volatile       bit	C2OUT		@ ((unsigned)&CM2CON0*8)+6;
static                bit	C2ON		@ ((unsigned)&CM2CON0*8)+7;

/* Definitions for CM2CON1 register */
static                bit	C2SYNC		@ ((unsigned)&CM2CON1*8)+0;
static                bit	T1GSS		@ ((unsigned)&CM2CON1*8)+1;
static                bit	C2HYS		@ ((unsigned)&CM2CON1*8)+2;
static                bit	C1HYS		@ ((unsigned)&CM2CON1*8)+3;
static                bit	T1ACS		@ ((unsigned)&CM2CON1*8)+4;
static volatile       bit	MC2OUT		@ ((unsigned)&CM2CON1*8)+6;
static volatile       bit	MC1OUT		@ ((unsigned)&CM2CON1*8)+7;

/* Definitions for ADCON0 register */
static                bit	ADON		@ ((unsigned)&ADCON0*8)+0;
static volatile       bit	GODONE		@ ((unsigned)&ADCON0*8)+1;
static                bit	CHS0		@ ((unsigned)&ADCON0*8)+2;
static                bit	CHS1		@ ((unsigned)&ADCON0*8)+3;
static                bit	CHS2		@ ((unsigned)&ADCON0*8)+4;
static                bit	CHS3		@ ((unsigned)&ADCON0*8)+5;
static                bit	VCFG		@ ((unsigned)&ADCON0*8)+6;
static                bit	ADFM		@ ((unsigned)&ADCON0*8)+7;

/* Definitions for OPTION register */
static          bank1 bit	PS0		@ ((unsigned)&OPTION*8)+0;
static          bank1 bit	PS1		@ ((unsigned)&OPTION*8)+1;
static          bank1 bit	PS2		@ ((unsigned)&OPTION*8)+2;
static          bank1 bit	PSA		@ ((unsigned)&OPTION*8)+3;
static          bank1 bit	T0SE		@ ((unsigned)&OPTION*8)+4;
static          bank1 bit	T0CS		@ ((unsigned)&OPTION*8)+5;
static          bank1 bit	INTEDG		@ ((unsigned)&OPTION*8)+6;
static          bank1 bit	RAPU		@ ((unsigned)&OPTION*8)+7;

/* Definitions for TRISA register */
static          bank1 bit	TRISA0		@ ((unsigned)&TRISA*8)+0;
static          bank1 bit	TRISA1		@ ((unsigned)&TRISA*8)+1;
static          bank1 bit	TRISA2		@ ((unsigned)&TRISA*8)+2;
static          bank1 bit	TRISA3		@ ((unsigned)&TRISA*8)+3;
static          bank1 bit	TRISA4		@ ((unsigned)&TRISA*8)+4;
static          bank1 bit	TRISA5		@ ((unsigned)&TRISA*8)+5;

/* Definitions for TRISC register */
static volatile bank1 bit	TRISC0		@ ((unsigned)&TRISC*8)+0;
static volatile bank1 bit	TRISC1		@ ((unsigned)&TRISC*8)+1;
static volatile bank1 bit	TRISC2		@ ((unsigned)&TRISC*8)+2;
static volatile bank1 bit	TRISC3		@ ((unsigned)&TRISC*8)+3;
static volatile bank1 bit	TRISC4		@ ((unsigned)&TRISC*8)+4;
static volatile bank1 bit	TRISC5		@ ((unsigned)&TRISC*8)+5;

/* Definitions for PIE1 register */
static          bank1 bit	TMR1IE		@ ((unsigned)&PIE1*8)+0;
static          bank1 bit	TMR2IE		@ ((unsigned)&PIE1*8)+1;
static          bank1 bit	C1IE		@ ((unsigned)&PIE1*8)+3;
static          bank1 bit	C2IE		@ ((unsigned)&PIE1*8)+4;
static          bank1 bit	CCP1IE		@ ((unsigned)&PIE1*8)+5;
static          bank1 bit	ADIE		@ ((unsigned)&PIE1*8)+6;

/* Definitions for PCON register */
static volatile bank1 bit	BOR		@ ((unsigned)&PCON*8)+0;
static volatile bank1 bit	POR		@ ((unsigned)&PCON*8)+1;

/* Definitions for OSCTUNE register */
static          bank1 bit	TUN0		@ ((unsigned)&OSCTUNE*8)+0;
static          bank1 bit	TUN1		@ ((unsigned)&OSCTUNE*8)+1;
static          bank1 bit	TUN2		@ ((unsigned)&OSCTUNE*8)+2;
static          bank1 bit	TUN3		@ ((unsigned)&OSCTUNE*8)+3;
static          bank1 bit	TUN4		@ ((unsigned)&OSCTUNE*8)+4;

/* Definitions for ANSEL register */
static          bank1 bit	ANS0		@ ((unsigned)&ANSEL*8)+0;
static          bank1 bit	ANS1		@ ((unsigned)&ANSEL*8)+1;
static          bank1 bit	ANS2		@ ((unsigned)&ANSEL*8)+2;
static          bank1 bit	ANS3		@ ((unsigned)&ANSEL*8)+3;
static          bank1 bit	ANS4		@ ((unsigned)&ANSEL*8)+4;
static          bank1 bit	ANS5		@ ((unsigned)&ANSEL*8)+5;
static          bank1 bit	ANS6		@ ((unsigned)&ANSEL*8)+6;
static          bank1 bit	ANS7		@ ((unsigned)&ANSEL*8)+7;

/* Definitions for WPUA register */
static          bank1 bit	WPUA0		@ ((unsigned)&WPUA*8)+0;
static          bank1 bit	WPUA1		@ ((unsigned)&WPUA*8)+1;
static          bank1 bit	WPUA2		@ ((unsigned)&WPUA*8)+2;
static          bank1 bit	WPUA4		@ ((unsigned)&WPUA*8)+4;
static          bank1 bit	WPUA5		@ ((unsigned)&WPUA*8)+5;

/* Definitions for IOCA register */
static          bank1 bit	IOCA0		@ ((unsigned)&IOCA*8)+0;
static          bank1 bit	IOCA1		@ ((unsigned)&IOCA*8)+1;
static          bank1 bit	IOCA2		@ ((unsigned)&IOCA*8)+2;
static          bank1 bit	IOCA3		@ ((unsigned)&IOCA*8)+3;
static          bank1 bit	IOCA4		@ ((unsigned)&IOCA*8)+4;
static          bank1 bit	IOCA5		@ ((unsigned)&IOCA*8)+5;

/* Definitions for SRCON0 register */
static          bank1 bit	SRCLKEN		@ ((unsigned)&SRCON0*8)+0;
static volatile bank1 bit	PULSR		@ ((unsigned)&SRCON0*8)+2;
static volatile bank1 bit	PULSS		@ ((unsigned)&SRCON0*8)+3;
static          bank1 bit	C2REN		@ ((unsigned)&SRCON0*8)+4;
static          bank1 bit	C1SEN		@ ((unsigned)&SRCON0*8)+5;
static          bank1 bit	SR0		@ ((unsigned)&SRCON0*8)+6;
static          bank1 bit	SR1		@ ((unsigned)&SRCON0*8)+7;

/* Definitions for SRCON1 register */
static          bank1 bit	SRCS2		@ ((unsigned)&SRCON1*8)+6;
static          bank1 bit	SRCS1		@ ((unsigned)&SRCON1*8)+7;

/* Definitions for ADCON1 register */
static          bank1 bit	ADCS0		@ ((unsigned)&ADCON1*8)+4;
static          bank1 bit	ADCS1		@ ((unsigned)&ADCON1*8)+5;
static          bank1 bit	ADCS2		@ ((unsigned)&ADCON1*8)+6;

// Configuration Mask Definitions
#define CONFIG_ADDR	0x2007
// Brown-Out reset 
#define BOREN		0x3FFF	// Enabled
#define BORXSLP		0x3EFF	// Enabled except in sleep
#define BORDIS		0x3DFF	// Disabled
// Internal Oscillator Frequency Select 
#define OSC_4MHZ	0x3F7F	// 4 MHz
#define OSC_8MHZ	0x3FFF	// 8 MHz
// Protection of flash memory 
#define PROTECT		0x3FBF	// Protected
#define UNPROTECT	0x3FFF	// Unprotected
// Master Clear Function 
#define MCLREN		0x3FFF	// Enabled
#define MCLRDIS		0x3FDF	// Disabled
// Power up timer 
#define PWRTEN		0x3FEF	// Enabled
#define PWRTDIS		0x3FFF	// Disabled
// Watchdog timer 
#define WDTEN		0x3FFF	// Enabled
#define WDTDIS		0x3FF7	// Disabled
// Oscillator configurations 
#define EXTCLK		0x3FFF	// External RC Clockout
#define EXTIO		0x3FFE	// External RC No Clock
#define INTCLK		0x3FFD	// Internal RC Clockout
#define INTIO		0x3FFC	// Internal RC No Clock
#define EC		0x3FFB	// EC
#define HS		0x3FFA	// HS
#define XT		0x3FF9	// XT
#define LP		0x3FF8	// LP

#endif
